LM2633

LM2633

AdvancedTwo-PhaseSynchronousTripleRegulatorControllerforNotebookCPUs

GeneralDescription

TheLM2633isafeature-richICthatcombinesthreeregu-latorcontrollers-twocurrentmodesynchronousbuckregu-latorcontrollersandalinearregulatorcontroller.

Thetwoswitchingregulatorcontrollersoperate180˚outofphase.ThisfeaturereducestheinputrippleRMScurrent,resultinginasmallerinputfilter.

Thefirstswitchingcontroller(Channel1)featuresanIntelmobileCPUcompatibleprecision5-bitdigital-to-analogcon-verterwhichprogramstheoutputvoltagefrom0.925Vto2.00V.ItisalsocompatiblewiththedynamicVIDrequire-ments.Thesecondswitchingcontroller(Channel2)isad-justablebetween1.25Vto6.0V.

Useofsynchronousrectificationandpulse-skipoperationatlightloadachieveshighefficiencyoverawideloadrange.Fixed-frequencyoperationcanbeobtainedbydisablingthepulse-skipmode.

Current-modefeedbackcontrolassuresexcellentlineandloadregulationandawideloopbandwidthforgoodre-sponsetofastloadtransientevents.CurrentmodecontrolisachievedthroughsensingtheVdsofthetopFETandthusanexternalsenseresistorisnotnecessary.

Apowergoodsignalisavailabletoindicatethegeneralhealthoftheoutputvoltages.

Auniquefeatureistheanalogsoft-startfortheswitchingcontrollersisindependentoftheslewrateoftheinputvolt-age.Thiswillmakethesoftstartbehaviormorepredictableandcontrollable.Aninternal5Vrailisavailableexternallyforboot-strapcircuitry(only)whenno5Visavailablefromothersources.

CurrentlimitforeitherofthetwoswitchingchannelsisachievedthroughsensingthetopFETVDSandthevalueisadjustable.Thetwoswitchingcontrollershaveunder-voltageandover-voltagelatchprotections,andthelinearregulatorhasunder-voltagelatchprotection.Under-voltagelatchcanbedisabledordelayedbyaprogrammableamountoftime.Theinputvoltagefortheswitchingchannelsrangesfrom5Vto30V,whichmakespossiblethechoiceofdifferentbatterychemistriesandoptions.

Features

GENERAL

nThreeregulatedoutputvoltagesn4.5Vto30VinputrangenPowergoodfunction

nInputunder-voltagelockoutnThermalshutdownnTinyTSSOPpackage

SWITCHINGSECTION

nTwochannelsoperating180˚outofphasenSeparateon/offcontrolforeachchannelnCurrentmodecontrolwithoutsenseresistornSkip-modeoperationavailable

nAdjustablecycle-by-cyclecurrentlimitnNegativecurrentlimit

nAnalogsoftstartindependentofinputvoltageslewratenPowergroundpinsseparatenOutputUVPandOVP

nProgrammableoutputUVPdelay

n250kHzswitchingfrequency(forVin<17V)nChannel1outputfrom0.925Vto2.00Vn±1.5%DACaccuracyfrom0˚Cto125˚Cn±1.7%initialtoleranceforChannel2nDynamicVIDchangereadynPowergoodflagsVIDchanges

nChannel2outputfrom1.3Vto6.0VLINEARSECTION

nOutputvoltageadjustable

n50mAmaximumdrivingcurrentnOutputUVP

n±2%initialtolerance

Applications

nPowersupplyforCPUsofnotebookPCsthatrequiretheSpeedStep™technique

nPowersupplyforinformationappliancesnGenerallowvoltageDC/DCbuckregulators

SpeedStep™isatrademarkofIntelCorporation.

©2001NationalSemiconductorCorporationDS200008www.national.com

LM2633ConnectionDiagram

TOPVIEW

PGOOD(Pin13)::Aconstantmonitorontheoutputvolt-ages.Itindicatesthegeneralhealthoftheregulators.Formoreinformation,seePowerGoodTruthTable(Table2)andPowerGoodFunctioninOperationDescriptions.GND(Pin16-17):Low-noiseanalogground.

G3(Pin18):Connecttothebaseorgateofthelinearregulatorpasstransistor.

OUT3(Pin19):Connecttotheoutputofthelinearregulator.FB3(Pin21):Thefeedbackinputforthelinearregulator,connectedtothecenteroftheexternalresistordivider.

COMP2(Pin22):Channel2compensationnetworkconnec-tion(it’stheoutputofthevoltageerroramplifier).

FB2(Pin23):ThefeedbackinputforChannel2.Connecttothecenteroftheoutputresistordivider.

SENSE2(Pin24):RemotesensepinofChannel2.Thispinisusedforskip-modeoperation.

ILIM2(Pin25):CurrentlimitthresholdsettingforChannel2.Itsinksataconstant10µAcurrent.AresistorisconnectedbetweenthispinandthetopMOSFETdrain.ThevoltageacrossthisresistoriscomparedwiththeVDSofthetopMOSFETtodetermineifanover-currentconditionhasoc-curredinChannel2.

KS2(Pin27):TheKelvinsenseforthedrainofthetopMOSFETofChannel2.

SW2(Pin29):Switch-nodeconnectionforChannel2,whichisconnectedtothesourceofthetopMOSFET.

HDRV2(Pin30):Topgate-driveoutputforChannel2.HDRV2isafloatingdriveoutputthatridesonSW2voltage.CBOOT2(Pin31):BootstrapcapacitorconnectionforChan-nel2topgatedrive.ItisthepositivesupplyrailforChannel2topgatedrive.

VDD2(Pin32):ThesupplyrailforChannel2bottomgatedrive.

LDRV2(Pin33):Bottomgate-driveoutputforChannel2.PGND2(Pin34):PowergroundforChannel2.VIN(Pin35):Theregulatorinputvoltagesupply.

VLIN5(Pin36):Theoutputoftheinternal5Vlinearregula-tor.Bypasstothegroundwitha1UFceramiccapacitor.Whenregulatorinputvoltageis5V,thispincanbetiedtoVINpintoimprovelight-loadefficiency.

PGND1(Pin38-39):PowergroundforChannel1.

LDRV1(Pin40-41):Bottomgate-driveoutputforChannel1.VDD1(Pin42):ThesupplyrailfortheChannel1bottomgatedrive.

CBOOT1(Pin43):BootstrapcapacitorconnectionforChan-nel1topgatedrive.ItisthepositivesupplyrailforChannel1topgatedrive.

HDRV1(Pin44):Topgate-driveoutputforChannel1.HDRV1isafloatingdriveoutputthatridesonSW1voltage.SW1(Pin45):Switch-nodeconnectionforChannel1,whichisconnectedtothesourceofthetopMOSFET.

KS1(Pin46):TheKelvinsenseforthedrainofthetopMOSFETofChannel1.

ILIM1(Pin48):CurrentlimitthresholdsettingforChannel1.Itsinksataconstant10µAcurrent.AresistorisconnectedbetweenthispinandthetopMOSFETdrain.ThevoltageacrossthisresistoriscomparedwiththeVDSofthetopMOSFETtodetermineifanover-currentconditionhasoc-curredinChannel1.

20000801

48-LeadTSSOP(MTD)OrderNumberLM2633MTDSeeNSPackageNumberMTD48

PinDescriptions

FB1(Pin1):ThefeedbackinputforChannel1.Connecttotheloaddirectly.

COMP1(Pin2):Channel1compensationnetworkconnec-tion(connectedtotheoutputofthevoltageerroramplifier).NC(Pins3,14,15,20,26,28,37and47):Nointernalconnection.

ON/SS1(Pin4):Addingacapacitortothispinprovidesasoft-startfunctionwhichminimizesinrushcurrentandoutputvoltageovershoot;Alowerthan0.8Vinput(open-collectortype)atthispinturnsoffChannel1;alsoifbothON/SS1andON/SS2pinsarebelow0.8V,thewholeICgoesintoshutdownmode.Thesoft-startcapacitorvoltagewilleventuallybechargedtoVINor6V,whicheverislower.

ON/SS2(Pin5):Addingacapacitortothispinprovidesasoft-startfunctionwhichminimizesinrushcurrentandoutputvoltageovershoot;Alowerthan0.8Vinput(open-collectortype)atthispinturnsoffChannel2;alsoifbothON/SS1andON/SS2pinsarebelow0.8V,thewholeICgoesintoshutdownmode.Thesoft-startcapacitorvoltagewilleventuallybechargedtoVINor6V,whicheverislower.

VID4-0(Pins6-10):Voltageidentificationcode.Eachpinhasaninternalpull-up.Theycanacceptopencollectorcompatible5-bitbinarycodefromtheCPU.ThecodetableisshowninTable3.

UV_DELAY(Pin11):Acapacitorfromthispintogroundadjuststhedelayfortheoutputunder-voltagelockout.

FPWM(Pin12):WhenFPWMislow,pulse-skipmodeop-erationatlightloadisdisabled.Theregulatorisforcedtooperateinconstantfrequencymode.

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BlockDiagramsLM26333

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LM2633www.national.com

20000886BlockDiagrams(Continued)4

BlockDiagrams(Continued)LM26335

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LM2633TABLE1.ShutDownLatchTruthTable

Input

ovp11

1

1

1

1

Σ=1

Allothercombinations

Note1:’Σ=1’meansatleastonevariableishigh.

Note2:’Fault’isthelogicORofUVLOandthermalshutdown.

Note3:’Cap’meansthepinhasacapacitorofappropriatevaluebetweenitandground.Note4:Positivelogicisused.

Note5:Formeaningsofthevariables,refertotheblockdiagrams.Note6:Ablankvaluemeans’don’tcare’.

Output

ch2on

fault000

1

00

Σ=11

1

capcapcap

ssto1

ssto2

uv_delay

latchoff

111110

ovp2uvp1uvp2uvplr

newvid00

ch1on

Σ=1Σ=11

TABLE2.PowerGoodTruthTable

Input

ovp11

1

1

1

1

1

π=0

1

1

Allothercombinations

Note7:″π=0″meansatleastonevariableislow.Note8:Positivelogicisused.

Note9:Ablankvaluemeans’don’tcare’.

Note10:Formeaningsofthevariables,refertotheblockdiagrams.

Output

ch1on

ch2on

fault

latchoff

PGOOD

0000000001

ovp2uvpg1uvpg2uvpglr

newvid

TABLE3.VIDCodeandDACOutput

VID411111111111111

VID311111111000000

VID211110000111100

VID111001100110011

VID010101010101010

DACVoltage(V)

NoCPU*

0.9250.9500.9751.0001.0251.0501.075

1.1001.1251.1501.1751.2001.225

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LM2633TABLE3.VIDCodeandDACOutput(Continued)

VID4110000000000000000

VID3001111111100000000

VID2001111000011110000

VID1001100110011001100

VID0101010101010101010

DACVoltage(V)

1.2501.275NoCPU

1.301.351.401.45

1.501.551.601.651.701.751.801.851.901.95

2.00*Thiscodeissetto0.900Vforconvenience.

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LM2633AbsoluteMaximumRatings

(Note11)ESDRating(Note14)AmbientStorageTemperatureRange

2kV

−65˚Cto+150˚C

IfMilitary/Aerospacespecifieddevicesarerequired,pleasecontacttheNationalSemiconductorSalesOffice/Distributorsforavailabilityandspecifications.VoltagesfromtheindicatedpinstoGND/PGND:VIN,KS1,KS2,SW1,SW2ILIM1,ILIM2VID0-VID4

VLIN,VDD1,VDD2,PGOODFB1,FB2,SENSE2,G3,FB3,OUT3CBOOT1CBOOT2ON/SS1,ON/SS2FPWM

PowerDissipation(TA=25˚C),(Note12)

JunctionTemperature

−0.3Vto31V−0.3Vto31V−0.3Vto5V−0.3Vto6V−0.3Vto6V

−0.3VtoSW1+7V−0.3VtoSW2+7V

−0.3Vto5V−0.3Vto7V

1.56W+150˚C

SolderingDwellTime,Temperature(Note13)Wave4sec,260˚CInfrared10sec,240˚CVaporPhase75sec,219˚C

OperatingRatings(Note11)

VIN(VINandVLIN5tiedtogether)

VIN(VINandVLIN5separate)JunctionTemperature1JunctionTemperature2VDD1,VDD2

4.5Vto5.5V5.0Vto30V0˚Cto+125˚C−40˚Cto+125˚C

4.5Vto5.5V

ElectricalCharacteristics

VCC=+15VunlessotherwiseindicatedundertheConditionscolumn.TypicalsandlimitsappearinginplaintypeapplyforTA=TJ=+25˚C.Limitsappearinginboldfacetypeapplyover0˚Cto+125˚C.SymbolSYSTEM∆Vout1_load∆Vout2_load∆VfbIvinChannel1Load

Regulation(Note17)Channel2Load

Regulation(Note17)LineRegulation(forthetwoswitchingregulators)InputSupplyCurrentwiththeSwitchingChannelsON

InputSupplyCurrentwiththeICShutDownVLIN5OutputVoltageILIM1andILIM2PinsSinkCurrent

NegativeCurrentLimit(SWxvsPGNDxvoltage)

SoftStartChargeCurrent

SoftStartSinkCurrentSoftStartONThresholdSoftStartTimeoutThreshold

UV_DELAYThresholdUV_DELAYSourceCurrent

VID4:0InternalPullUpCurrent

(Note20)

VLIN5=5V(Note21)

1.0

InUVLOorthermalshutdown

0.5

VCOMP1movesfrom0.5Vto1.5V,VID4:0=01101

VCOMP2movesfrom0.5Vto1.5V5.0V≤VIN≤30V,VID4:0=01101VFB=0.9V,noVLIN5DCCurrent(Note18)

VON/SS1=VON/SS2=0V(Note19)

IVLIN5=0to25mA,5.5V4.78

01.52

mVmVmV

Parameter

Conditions

Min

Typ

Max

Units

1.52.4mA

Ivin_sdVvlin5Iilim_posVilim_neg105.010

185.312

µAVµA

45mV

Iss_scIss_skVss_onVsstoVuvdIdelayIvid2.2521.23.52.156

5µAµAVVV

9.013

µAµA

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LM2633ElectricalCharacteristics

SymbolSYSTEMVuvlo_thrVINUnder-voltageLockout(UVLO)Threshold

VINUVLOHysteresisChannel1VOUTUnder-voltageShutdownLatchThreshold

(MeasuredattheFB1)Channels2and3VOUTUndervoltageShutdownLatchThreshold

(MeasuredattheFB2andFB3)

VOUTOvervoltageShutdownLatch

ThresholdforChannel1(MeasuredattheFB1)VOUTOvervoltageShutdownLatch

ThresholdforChannel2(MeasuredattheFB2)VOUTLowRegulationComparatorEnableThresholdforChannels1and2

HysteresisofLow

RegulationComparatorRegulatorWindowDetectorThresholds(PGOODfromHightoLow)

RegulatorWindowDetectorThresholds(PGOODfromLowtoHigh)

CBOOTLeakageCurrent

HDRV1SourceCurrentHDRV1SinkCurrentLDRV1SourceCurrentLDRV1SinkCurrentHDRV1High-SideFETOn-ResistanceLDRV1High-SideFETOn-ResistanceLDRV1Low-SideFETOn-Resistance

Parameter

(Continued)

VCC=+15VunlessotherwiseindicatedundertheConditionscolumn.TypicalsandlimitsappearinginplaintypeapplyforTA=TJ=+25˚C.Limitsappearinginboldfacetypeapplyover0˚Cto+125˚C.

Conditions

RisingEdge

4.2300

VID4:0=01100

73

80

83

%VOUT4.5

VmV

Min

Typ

Max

Units

Vuvlo_hysVuvp1Vuvp2,3VID4:0=01100

76

80

86

%VOUTVovp1110114119

%VOUTVovp2109112115

%VOUTVlreg_thr91.5

%VOUTVlreg_hysVpwrbad7

85

(Note22)

110

88

%VOUT%VOUT112

119

Vpwrgd909397

%VOUTGateDrive(ForChannel1SwitchingRegulatorController)Iboot1VCBOOT1=7V

VHDRV1=VSW1=0V,VCBOOT1=5VVHDRV1=5VVLDRV1=0VVLDRV1=5V

1001.21.01.22.01.84tbd0.5

nAAAAAΩΩΩ

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LM2633ElectricalCharacteristics

SymbolIboot2Parameter

CBOOTLeakageCurrent

HDRV2SourceCurrentHDRV2SinkCurrentLDRV2SourceCurrentLDRV2SinkCurrentHDRV2FETOn-ResistanceLDRV2FETOn-Resistance

OscillatorFoscToff_minTon_minIfb1Ifb2Ifb3Icomp1,Icomp2Vcomp_maxGm∆VdacOscillatorFrequencyMinimumOff-TimeMinimumOn-TimeFeedbackInputBiasCurrent,Channel1FeedbackInputBiasCurrent,Channel2FeedbackInputBiasCurrent,Channel3COMPOutputSinkCurrent

COMPPinMaximumVoltage

TransconductanceChannel1DACOutputVoltageAccuracy

(Continued)

VCC=+15VunlessotherwiseindicatedundertheConditionscolumn.TypicalsandlimitsappearinginplaintypeapplyforTA=TJ=+25˚C.Limitsappearinginboldfacetypeapplyover0˚Cto+125˚C.

Conditions

VCBOOT2=7V

VHDRV2=VSW2=0V,VCBOOT2=5VVHDRV2=5VVLDRV2=0VVLDRV2=5V

Min

Typ

Max

Units

GateDrive(ForChannel2SwitchingRegulatorController)

100tbdtbdtbdtbdtbdtbd

nAAAAAΩΩ

225250400220

275kHznsns

ErrorAmplifier

VFB1=2.4VVFB2=1.36VVFB3=1.36V

VFB1=150%ofmeasured1.4VDAC,VFB2=150%ofmeasuredbandgap,VCOMP1=VCOMP2=1V

tbd

551870

µAnAnA

60µA

1.96576

Vµmho

DACOutputandVFB2VCOMP1=1V,DACcodesfrom1.3Vto1.6V

VCOMP1=1V,DACcodesfrom0.925Vto1.25Vandfrom1.65Vto2.00V

Vfb2Channel2DCOutputVoltageAccuracyChannel3DCOutputVoltageAccuracyG3SinkCurrentG3MinimumSourceCurrent

G3MaximumVoltage

COMP2pinfrom0.5Vto1.8V

−1.5

1.5

%

−1.7

1.7

1.2171.2381.259V

LinearRegulatorControllerVfb3Vg3_skIg3_scVg3_max1.215

1.2420203.6

1.265

VµAmAV

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LM2633ElectricalCharacteristics

SymbolVihParameter

MinimumHighLevelInputVoltage(FPWM,VID0-VID4)

MaximumLowLevelInputVoltage(FPWM,ON/SS1,ON/SS2,VID0-VID4)

PGOODOutputHighCurrent

PGOODOutputLowVoltage

(Continued)

VCC=+15VunlessotherwiseindicatedundertheConditionscolumn.TypicalsandlimitsappearinginplaintypeapplyforTA=TJ=+25˚C.Limitsappearinginboldfacetypeapplyover0˚Cto+125˚C.

Conditions

Min

Typ

Max

Units

LogicInputsandOutputs

2.0

V

Vil0.8V

Ioh_pgVol_pgPGOOD=5.7V(Note23)PGOODSinking20µA

50.3

µAV

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LM2633ElectricalCharacteristics

VCC=+15VunlessotherwiseindicatedundertheConditionscolumn.TypicalsandlimitsappearinginplaintypeapplyforTA=TJ=+25˚C.Limitsappearinginboldfacetypeapplyover−40˚Cto+125˚C.SymbolSYSTEM∆Vout1_load∆Vout2_load∆VfbIvinChannel1Load

Regulation(Note17)Channel2Load

Regulation(Note17)LineRegulation(forthetwoswitchingregulators)InputSupplyCurrentwiththeSwitchingChannelsON

InputSupplyCurrentwiththeICShutDownVLIN5OutputVoltageILIM1andILIM2PinsSinkCurrent

NegativeCurrentLimit(SWxvsPGNDxvoltage)

SoftStartChargeCurrent

SoftStartSinkCurrentSoftStartONThresholdSoftStartTimeoutThreshold

UV_DELAYThresholdUV_DELAYSourceCurrent

VID4:0InternalPullUpCurrent

VINUnder-voltageLockout(UVLO)Threshold

VINUVLOHysteresisChannel1VOUTUnder-voltageShutdownLatchThreshold

(MeasuredattheFB1)Channels2and3VOUTUndervoltageShutdownLatchThreshold

(MeasuredattheFB2andFB3)

VOUTOvervoltageShutdownLatch

ThresholdforChannel1(MeasuredattheFB1)

VID4:0=01100

72

80

84

%VOUTRisingEdge

4.2300

4.6

VmV

(Note20)

VLIN5=5V(Note21)

1.0

InUVLOorthermalshutdown

0.5

VCOMP1movesfrom0.5Vto1.5V,VID4:0=01101

VCOMP2movesfrom0.5Vto1.5V5.0V≤VIN≤30V,VID4:0=01101VFB=0.9V,noVLIN5DCCurrent(Note18)

VON/SS1=VON/SS2=0V(Note19)

IVLIN5=0to25mA,5.5V4.77

01.52

mVmVmV

Parameter

Conditions

Min

Typ

Max

Units

1.52.5mA

Ivin_sdVvlin5Iilim_posVilim_neg105.010

185.313

µAVµA

45mV

Iss_scIss_skVss_onVsstoVuvdIdelayIvidVuvlo_thr2.2521.23.52.156

5µAµAVVV

9.013

µAµA

Vuvlo_hysVuvp1Vuvp2,3VID4:0=01100

75

80

87

%VOUTVovp1109114120

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LM2633ElectricalCharacteristics

SymbolSYSTEMVovp2VOUTOvervoltageShutdownLatch

ThresholdforChannel2(MeasuredattheFB2)VOUTLowRegulationComparatorEnableThresholdforChannels1and2

HysteresisofLow

RegulationComparatorRegulatorWindowDetectorThresholds(PGOODfromHightoLow)

RegulatorWindowDetectorThresholds(PGOODfromLowtoHigh)

CBOOTLeakageCurrent

HDRV1SourceCurrentHDRV1SinkCurrentLDRV1SourceCurrentLDRV1SinkCurrentHDRV1High-SideFETOn-ResistanceLDRV1High-SideFETOn-ResistanceLDRV1Low-SideFETOn-Resistance

Parameter

(Continued)

VCC=+15VunlessotherwiseindicatedundertheConditionscolumn.TypicalsandlimitsappearinginplaintypeapplyforTA=TJ=+25˚C.Limitsappearinginboldfacetypeapplyover−40˚Cto+125˚C.

Conditions

Min

Typ

Max

Units

108112116

%VOUTVlreg_thr91.5

%VOUTVlreg_hysVpwrbad7

84

(Note22)

109

88

%VOUT%VOUT112

120

Vpwrgd899398

%VOUTGateDrive(ForChannel1SwitchingRegulatorController)Iboot1VCBOOT1=7V

VHDRV1=VSW1=0V,VCBOOT1=5VVHDRV1=5VVLDRV1=0VVLDRV1=5V

1001.21.01.22.01.84tbd0.5

nAAAAAΩΩΩ

GateDrive(ForChannel2SwitchingRegulatorController)Iboot2CBOOTLeakageCurrent

HDRV2SourceCurrentHDRV2SinkCurrentLDRV2SourceCurrentLDRV2SinkCurrentHDRV2FETOn-ResistanceLDRV2FETOn-Resistance

OscillatorFoscToff_minTon_minIfb1OscillatorFrequencyMinimumOff-TimeMinimumOn-TimeFeedbackInputBiasCurrent,Channel1

VFB1=2.4V

225

250400220

275

kHznsns

VCBOOT2=7V

VHDRV2=VSW2=0V,VCBOOT2=5VVHDRV2=5VVLDRV2=0VVLDRV2=5V

100tbdtbdtbdtbdtbdtbd

nAAAAAΩΩ

ErrorAmplifier

55

µA

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LM2633ElectricalCharacteristics

SymbolErrorAmplifierIfb2Ifb3Icomp1,Icomp2Vcomp_maxGm∆VdacFeedbackInputBiasCurrent,Channel2FeedbackInputBiasCurrent,Channel3COMPOutputSinkCurrent

COMPPinMaximumVoltage

TransconductanceChannel1DACOutputVoltageAccuracy

Parameter

(Continued)

VCC=+15VunlessotherwiseindicatedundertheConditionscolumn.TypicalsandlimitsappearinginplaintypeapplyforTA=TJ=+25˚C.Limitsappearinginboldfacetypeapplyover−40˚Cto+125˚C.

Conditions

VFB2=1.36VVFB3=1.36V

VFB1=150%ofmeasured1.4VDAC,VFB2=150%ofmeasuredbandgap,VCOMP1=VCOMP2=1V

tbdMin

Typ

Max

Units

1870

nAnA

91µA

1.96576

Vµmho

DACOutputandVFB2VCOMP1=1V,DACcodesfrom1.3Vto1.6V

VCOMP1=1V,DACcodesfrom0.925Vto1.25Vandfrom1.65Vto2.00V

Vfb2Channel2DCOutputVoltageAccuracyChannel3DCOutputVoltageAccuracyG3SinkCurrentG3MinimumSourceCurrent

G3MaximumVoltageMinimumHighLevelInputVoltage(FPWM,VID0-VID4)

MaximumLowLevelInputVoltage(FPWM,ON/SS1,ON/SS2,VID0-VID4)

PGOODOutputHighCurrent

PGOODOutputLowVoltage

PGOOD=5.7V(Note23)PGOODSinking20µA

50.3

COMP2pinfrom0.5Vto1.8V

−2.0

2.0

%

−2.2

2.2

1.2121.2381.264V

LinearRegulatorControllerVfb3Vg3_skIg3_scVg3_maxVih1.209

1.2420203.6

1.271

VµAmAV

LogicInputsandOutputs

2.2

V

Vil0.7V

Ioh_pgVol_pgµAV

Note11:Absolutemaximumratingsindicatelimitsbeyondwhichdamagetothedevicemayoccur.OperatingRatingsareconditionsunderwhichoperationofthedeviceisguaranteed.Forguaranteedperformancelimitsandassociatedtestconditions,seetheElectricalCharacteristicstable.

Note12:MaximumallowablepowerdissipationiscalculatedbyusingPDMAX=(TJMAX-TA)/θJA,whereTJMAXisthemaximumjunctiontemperature,TAistheambienttemperatureandθJAisthejunction-to-ambientthermalresistanceofthespecifiedpackage.The1.56Wratingresultsfromusing150˚C,25˚C,and80˚C/WforTJMAX,TA,andθJArespectively.AθJAof90˚C/Wrepresentstheworst-caseconditionofnoheatsinkingofthe48-pinTSSOP.Heatsinkingallowsthesafedissipationofmorepower.TheAbsoluteMaximumpowerdissipationshouldbederatedby12.5mWper˚Cabove25˚Cambient.TheLM2633activelylimitsitsjunctiontemperaturetoabout150˚C.

Note13:Fordetailedinformationonsolderingplasticsmall-outlinepackages,refertothePackagingDatabookavailablefromNationalSemiconductorCorporation.Note14:ExceptforILIM1andILIM2pins,whichare1.5kV.Fortestingpurposes,ESDwasappliedusingthehuman-bodymodel,a100pFcapacitordischargedthrougha1.5kΩresistor.

Note15:AtypicalisthecenterofcharacterizationdatatakenwithTA=TJ=25˚C.Typicaldataarenotguaranteed.

Note16:Alllimitsareguaranteed.Allelectricalcharacteristicshavingroom-temperaturelimitsaretestedduringproductionwithTA=TJ=25˚C.Allhotandcoldlimitsareguaranteedbycorrelatingtheelectricalcharacteristicstoprocessandtemperaturevariationsandapplyingstatisticalprocesscontrol.Note17:ThistestsimulatesheavyloadconditionbychangingCOMPpinvoltage.

Note18:ThisparameterindicateshowmuchcurrenttheLM2633isdrawingfromtheinputsupplywhenitisfunctioningbutnotdrivingexternalMOSFETsorabipoloartransistor.

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LM2633ElectricalCharacteristics

(Continued)

Note19:ThisparameterindicateshowmuchcurrenttheLM2633isdrawingfromtheinputsupplywhenitiscompletelyshutoff.Note20:WhenON/SS1,2pinsarechargedabovethisvoltage,theundervoltageprotectionfeatureisenabled.Note21:Abovethisvoltage,theunder-voltageprotectionisenabled.Note22:Thisisthesameasover-voltageprotectionthreshold.

Note23:ThisistheamountofcurrentPGOODsinkswhenPGOODishighandisforcedtothevoltageindicated

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20000804TypicalApplication16

LM2633TypicalApplication

IDC1C2C3C4C5C6C7C8C9C10C11C12C13C14C15C16C17C18C19D1D2D3D4L1L2Q1Q2Q3Q4Q5R1R2R3R4R5R6R7R8R9R10R11R12R13R14U1

CEPH149-1R6MCCDRH127-100MCIRF7805IRF7805IRF7807IRF7807MMBT2222ALT1CRCW0805100JCRCW0805104JCRCW08051002FCRCW08054752FCRCW08052612FCRCW08052872FCRCW0805243JCRCW0805512JCRCW0805683JCRCW0805562JCRCW08051002FCRCW08051002FCRCW0805100JCRCW0805104JLM2633M

Number25SP56M

T510E108M004AST510E108M004ASVJ1206S105MXJACVJ1206S105MXJACVJ0805Y104MXAABVJ0805Y153MXJABVJ0805Y103MXAABVJ0805Y103MXAABVJ0805Y222MXJABVJ0805Y681MXJABVJ0805Y472MXJABVJ0805Y472MXJABVJ0805Y821MXJABVJ0805A221MXAABVJ0805Y474MXJABVJ1206S105MXJACVJ0805Y104MXJACVJ0805Y104MXJACBAT54BAT54

(Continued)

TABLE4.BillofMaterialsforTypicalApplicationCircuit

Type

Capacitor,OSCONCapacitor,TantalumCapacitor,TantalumCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicCapacitor,CeramicDiode,SchottkyDiode,SchottkyDiode,SchottkyDiode,SchottkyInductor,PowerInductor,PowerMOSFET,N-CHANMOSFET,N-CHANMOSFET,N-CHANMOSFET,N-CHANBJT,NPNResistorResistorResistorResistorResistorResistorResistorResistorResistorResistorResistorResistorResistorResistorIC

14.6x14.6mm212x12mmSO-8SO-8SO-8SO-8SOT-2308050805080508050805080508050805080508050805080508050805TSSOP-48

2Size

Radial,ΦxL=10.5x10.5mm27.3x6.0x3.6mm37.3x6.0x3.6mm31206120608050805080508050805080508050805080508050805120608050805SOT-23SOT-23

Parameters25V,56µF,25mΩ,3.2A

4V,1mF,18mΩ4V,1mF,18mΩ16V,1µF,X7S16V,1µF,X7S50V,0.1µF,X7R16V,0.015µF,X7R50V,0.01µF,X7R50V,0.01µF,X7R16V,2200pF,X7R16V,680pF,X7R16V,4700pF,X7R16V,4700pF,X7R16V,820pF,X7R50V,220pF,X7R16V,0.47µF,X7R16V,1µF,X7S16V,0.1µF,X7R16V,0.1µF,X7R30V,200mA30V,200mA

Qt.33111111111111111111111

VendorSanyoKemetKemetVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishay(optional)(optional)SumidaSumidaIRIRIRIRMotorolaVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayVishayNational

1.6µH,15.5A,1.5mΩ10µH,5.4A,21.6mΩ30V,10mΩ@4.5V30V,10mΩ@4.5V30V,25mΩ@4.5V30V,25mΩ@4.5V40V,600mA10Ω,5%100kΩ,5%10.0kΩ,1%47.5kΩ,1%26.1kΩ,1%28.7Ω,1%24kΩ,5%5.1kΩ,5%68kΩ,5%5.6kΩ,5%10.0kΩ,1%10.0kΩ,1%10Ω,5%100kΩ,5%3-in-1control

1112111111111111111111

(Forperformance,seeTypicalPerformanceCurves)

17www.national.com

LM2633TypicalPerformanceCharacteristics

EfficiencyvsLoadCurrent(Ch1,TypicalApplication)

EfficiencyvsLoadCurrent

(Ch2,TypicalApplication,FPWM=0)

200008A120000898

EfficiencyvsLoadCurrent

(Ch2,TypicalApplication,FPWM=1)

SwitchingFrequencyvsLoadCurrent

2000089920000890

PWMFrequencyvsTemperatureErrorAmplifierTransconductancevsTemperature

200008A3200008A4

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LM2633TypicalPerformanceCharacteristics

VLIN5VoltagevsTemperature

(Continued)

Ch2ReferenceVoltagevsTemperature

20000894

200008B5

CurrentSourcingCapabilityof

PinG3vsItsVoltage

DACVoltagevsTemperature(Ch1)

200008A6

20000897

BiasCurrentofPinILMxvsTemperature

Force-PWMOperation

(TypicalApplication,Ch1Load=120mA)

200008A2

200008A5

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LM2633TypicalPerformanceCharacteristics

Skip-ModeOperation

(TypicalApplication,Ch1Load=120mA)

(Continued)

SoftStartwithConstantLoadCurrent

200008B3

20000892

SoftStartUnderNoLoad(Ch1,TypicalApplication)LoadTransientResponse

(Ch1,TypicalApplication,VOUT1=1.6V)

200008B4200008A9

CurrentLimitandUVP

Control-OutputBodePlot

(Ch1,TypicalApplication,VIN=8V,NoLoad)

20000891

20000893

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LM2633TypicalPerformanceCharacteristics

LoopBodePlot(Ch1,TypicalApplication,VIN=8V,

VOUT1=1.6V,NoLoad,

Compensation:C14=390pF,R9=100k,C15=150pF,

R10=8.2k)

(Continued)

Control-OutputBodePlot

(Ch2,TypicalApplication,VIN=8V,NoLoad)

200008B120000896

LoopBodePlot(Ch2,TypicalApplication,VIN=8V,No

Load,

Compensation:C10=5.6nF,R7=30k,C11=560pF,

R8=5.1k)

200008B2

21www.national.com

LM2633OperationDescriptions

General

TheLM2633isacombinationofthreevoltageregulatorcontrollers.Amongthem,twoareswitchingregulatorcontrol-lersandoneisalinearregulatorcontroller.Thetwoswitch-ingcontrollers,Channel1andChannel2,operate180˚outofphase.Theycanbeindependentlyenabledanddisabled.Thelinearcontroller,orChannel3,isdisabledonlywhenbothswitchingchannelsaredisabled.Channel1outputvoltageissetbyaninternalDAC,whichacceptsa5-bitVIDcodefrompins6through10.Channels2and3outputvoltagesareadjustedwithavoltagedivider.Bothswitchingchannelsaresynchronousandemploypeakcurrentmodecontrolscheme.Protectionfeaturesincludeover-voltageprotection(Ch1and2),under-voltageprotection(allchan-nels),andpositiveandnegativepeakcurrentlimit(Ch1and2).UVPfunctioncanbedelayedbyanarbitraryamountoftime.Inputvoltagetotheswitchingregulatorscanrangefrom4.5Vto30V.Thelinearcontrollercangenerateamaxi-mum3.8Vgate/basedrivevoltage.WithanexternalNPNtransistor,outputvoltagecangoupto3.0V.Thepowergoodfunctionalwaysmonitorsallthreeoutputvoltages.

SoftStart

IftheON/SSxpinisconnectedtogroundinsteadoftoacapacitor,thecorrespondingchannelisturnedoffandwillnotstartup.

AssumetheON/SSxpinisconnectedtoacapacitorandtherestofthecircuitissetupcorrectly.Whentheinputvoltagerisesabovethe4.2Vthreshold,theinternalcircuitryispow-eredon,theON/SSxpinshouldbealreadyheldat1.1V,anda2µAcurrentstartstochargethecapacitorconnectedbe-tweentheON/SSxpinandground.WhentheON/SSxpinvoltageexceeds1.2V,thecorrespondingchannelisturnedon.AMIN_ON_TIMEcomparatorgeneratesthesoftstartPWMpulses.AstheON/SSxpinvoltagerampsup,thedutycyclegrows,causingtheoutputvoltagetorampup.Duringthistime,theerroramplifieroutputvoltageisclampedat0.8V,andthedutycyclegeneratedbythePWMcomparatorisignored.Whenthecorrespondingoutputvoltageexceeds99%ofthesettargetvoltage,themodeofthechanneltransitionsfromsoftstarttooperating.Asaresult,thehighclampattheoutputoftheerroramplifierisswitchedto2V.Beyondthispoint,oncethePWMpulsesgeneratedbythePWMcomparatorarewiderthanthatgeneratedbytheMI-N_ON_TIMEcomparator,thePWMcomparatortakesoverandstartstoregulatetheoutputvoltage.Thatis,peakcurrentmodecontrolnowtakesplace.

Thespeedatwhichthedutycyclegrowsdependsonthecapacitanceofthesoftstartcapacitor.Thehighertheca-pacitance,theslowerthespeed.However,thatspeedisindependentofhowfasttheinputvoltagerises.Thatisbecausetherampsignalusedtogeneratethesoftstartdutycyclehasaslopeproportionaltoinputvoltage,makingtheproductofdutycycleandinputvoltageavaluethatisinde-pendentofinputvoltage.ThisfeaturemakesthesoftstartprocessmorepredictableandreliablebecausewhethertheinputpowersupplygoesthroughasoftstartprocessorisappliedabruptlydoesnotaffecttheLM2633softstart.

Duringsoftstart,under-voltageprotectionisdisabled.Butover-voltageprotectionandcurrentlimitareinplace.

WhentheON/SSxpinvoltageexceeds3.5V,asoftstarttimeoutsignal(sstox)willbeissued.Thissignalenablestheunder-voltageprotection.SeetheUnder-VoltageProtectionsection.

ShutdownMode

IfbothON/SSxpinsarepulledlow,theICwillbeinshutdownmode.Bothtopgate-drivesofthetwoswitchingchan-nelsareturnedoffwhilebothbottomgate-drivesremainon.Thelinearchannelisalsodisabled.

ThesamethinghappenstothegatedriveswhentheinputvoltageisbroughtbelowtheUVLOthreshold.

TurningOffaSwitchingChannel

AswitchingchannelcanbeturnedoffbypullingitsON/SSxpinbelowabout1.1V.UpondetectingalowlevelonON/SSxpin,thecorrespondingtopgate-drivewillbeturnedoffandthebottomgate-drivewillbeturnedon.

Inahighcurrentapplication,itmaybenecessarytotakespecialmeasurestomakesurethattheoutputvoltagedoesnotgotoonegativeduringshutdown.Oneofthosemea-suresistoaddaSchottkydiodeinparallelwithoutputcapacitors.Anothermeasureistofinetunethepowerstageparameterssuchasinductanceandcapacitancevalues.FaultState

Whenevertheinputvoltagebecomestoolow(lessthanabout3.9V),ortheICistoohotandentersthermalshutdownmode,a’fault’signalwillbegeneratedinternally.ThissignalwilldischargethecapacitorconnectedbetweentheON/SSxpinandgroundwith3µAofcurrentuntilthepinreaches1.1V.Theswitchingchannelswillbeturnedoffuponseeingthissignal.

Inthefaultstate,OVPandUVParedisabledandshutdownlatchisreleased.

Force-PWMMode

Thismodeappliestobothswitchingchannelssi-multaneously.Theforce-PWMmodeisactivatedbypullingtheFPWMpintologiclow.Inthismode,thetopFETandthebottomFETgatesignalsarealwayscomplementarytoeachother.The0-CROSSING/NEGATIVECURRENTLIMITcomparatorwillbesettodetectthenegativecurrentlimit.Inforce-PWMmode,theregulatoralwaysoperatesinContinu-ousConductionMode(CCM)anditssteady-statedutycycle(approximatelyVOUT/VIN)isalmostindependentofload.Theforce-PWMmodeisgoodforapplicationswherefixedswitchingfrequencyisrequired.Italsooffersthefastestloadtransientresponse.

Inforce-PWMmode,thetopFEThastobeturnedonforaminimumof220nseachcycle.However,whentherequireddutycycleislessthantheminimumvalue,theskipcompara-torwillbeactivatedandpulseswillbeskippedtomaintainregulation.

SkipComparator

WhenevertheCOMPxpinvoltagegoesbelowthe0.5Vthreshold,thePWMcycleswillbe’skipped’untilthatvoltageagainexceedsthethreshold.

Pulse-SkipMode

ThismodeisactivatedbypullingtheFPWMpintoaTTL-compatiblelogichighandappliestobothswitchingchannelssimultaneously.Inthismode,the0-CROSSING/NEGATIVECURRENTLIMITcomparatordetectsthebottom

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LM2633OperationDescriptions

(Continued)

FETcurrent.OncethebottomFETcurrentflowsfromdraintosource,thebottomFETwillbeturnedoff.Thispreventsnegativeinductorcurrent.Inforce-PWMoperation,thein-ductorcurrentisallowedtogonegative,sotheregulatorisalwaysinContinuousConductionMode(CCM),nomatterwhattheloadis.InCCM,thesteady-statedutycycleisalmostindependentoftheload,andisroughlyVOUTdividedbyVIN.Inpulse-skipmode,theregulatorentersDiscontinu-ousConductionMode(DCM)underlightload.OncetheregulatorentersDCM,itssteady-statedutycycledroopsastheloadcurrentdecreases.TheregulatoroperatesinDCMPWMmodeuntilitsdutycyclefallsbelow85%oftheCCMdutycycle,whentheMIN_ON_TIMEcomparatortakesover.Itforces85%CCMdutycyclewhichcausestheoutputvoltagetocontinuouslyriseandCOMPxpinvoltage(erroramplifieroutputvoltage)tocontinuouslydroop.WhentheCOMPxpinvoltagedipsbelow0.5V,theCYCLE_SKIPcom-paratortoggles,causingthepresentswitchingcycletobe’skipped’,i.e.,bothFETsremainoffduringthewholecycle.AslongastheCOMPxpinvoltageisbelow0.5V,noswitch-ingoftheFETswillhappen.Asaresult,theoutputvoltagewilldroop,andtheCOMPxpinvoltagewillrise.WhentheCOMPxpingoesabove0.5V,theCYCLE_SKIPcomparatorflipsandallowsa85%CCMdutycyclepulsetohappen.IftheloadcurrentissosmallthatthissinglepulseisenoughtobringoutputvoltageuptosuchalevelthattheCOMPxpindropsbelow0.5Vagain,thepulseskippingwillhappenagain.OtherwiseitmaytakeanumberofconsecutivepulsestobringtheCOMPxpinvoltagedownto0.5Vagain.Astheloadcurrentincreases,ittakesmoreandmoreconsecutivepulsestodischargetheCOMPxvoltageto0.5V.Whentheloadcurrentissohighthatthedutycycleexceedsthe85%CCMdutycycle,thenpulse-skippingdisappears.Inpulse-skipmode,thefrequencyoftheswitchingpulsesde-creasesastheloadcurrentdecreases.

TheLM2633needstosensetheoutputvoltagesdirectlyinthepulse-skipmodeoperation.ForChannel1thisisrealizedthroughtheFB1pin.ForChannel2,itisrealizedbycon-nectingSENSE2pintotheoutput.

TheLM2633pulse-skipmodehelpsthelightloadefficiencyfortworeasons.First,itdoesnotturnonthebottomFET,thiseliminatescirculatingenergyandreducesgatedrivepowerloss.Second,thetopFETisonlyturnedonwhennecessary,ratherthaneverycycle,whichalsoreducesgatedrivepowerloss.

CurrentSensingandCurrentLimiting

Sensingoftheinductorcurrentforfeedbackcontrolisac-complishedthroughsensingthedrain-sourcevoltageofthetopFETwhenitisturnedon.ThereisaleadingedgeblankingcircuitrythatforcesthetopFETtobeonforatleast160ns.Beyondthisminimumontime,theoutputofthePWMcomparatorisusedtoturnoffthetopFET.TheblankingcircuitryisbeingusedtoblankoutthenoiseassociatedwiththeturningonofthetopFET.

CurrentlimitisimplementedusingthesameVdsinformation.SeeFigure1.

20000805

FIGURE1.CurrentLimitMethod

Thereisa10µAcurrentsinkontheILIMxpin.WhenanexternalresistorisconnectedbetweenILIMxpinandtopFETdrain,aDCvoltageisestablishedbetweenthetwonodes.WhenthetopFETisturnedon,thevoltageacrosstheFETisproportionaltotheinductorcurrent.Iftheinductorcurrentistoohigh,SWxpinvoltagewillbelowerthantheILIMxvoltage,causingthecomparatortotoggleandthusthetopFETwillbeturnedoffimmediately.ThecomparatorisdisabledwhenthetopFETisturnedoffandduringtheleadingedgeblankingtime.

NegativeCurrentLimit

ThenegativecurrentlimitisputinplacetoensurethattheinductorwillnotsaturateduringanegativecurrentflowandcauseexcessivecurrenttoflowthroughthebottomFET.ThenegativecurrentlimitisrealizedthroughsensingthebottomFETVds.AninternalreferencevoltageisusedtocomparewiththebottomFETVdswhenitison.UponseeingtoohighaVds,thebottomFETwillbeturnedoff.ThenegativecurrentlimitisactivatedinforcePWMmode,orinthecaseofChannel1,alsowheneverthereisadynamicVIDchange.ActiveFrequencyControl

Astheinput/outputvoltagedifferentialincreases,theontimeofthetopFETasregulatedbythefeed-backcontrolcircuitrymayapproachtheminimumvalue,i.e.theblankingtime.Thatwillcauseunstableoperationssuchaspulseskippingandunevendutycycles.Toavoidsuchanissue,theLM2633isdesignedinsuchawaythatwheninputvoltagerisesaboveabout17V,thePWMfrequencystartstodroop.Thefrequencydroopsfairlylinearlywiththeinputvoltage.Seetypicalcurves.ThetheoreticalequationforPWMfre-quencyisƒ=min(1,17V/VIN)x250kHz.

ThemainimpactofthisshiftinPWMfrequencyistheinductorripplecurrentandoutputripplevoltage.Regulatordesignshouldtakethisintoaccount.

ShutdownLatchState

Thisstateistypicallycausedbyanoutputundervoltageorovervoltageevent.Inthisstate,bothswitchingchannelshavetheirtopFETsturnedoff,andtheirbottomFETsturnedon.Thelinearchannelisnotaffected.

Therearetwomethodstoreleasethesystemfromthelatchstate.Oneistocreateafaultstate(seethecorrespondingsection)byeitherbringingdowntheinputvoltagetobelow3.9VUVLOthresholdandthenbringingitbacktoabove4.2V,orsomehowbycausingthesystemtoenterthermalshutdown.AnothermethodistopullbothON/SSxpinsbelow0.8Vandthenreleasethem.

Afterthelatchisreleased,thetwoswitchingchannelswillgothroughthenormalsoftstartprocess.Thelinearchannel

23

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LM2633OperationDescriptions

(Continued)

PowergoodupperlimitisthesameasthatoftheOVPfunction.

Incases2and3above,ifthecorrespondingoutputvolt-age(s)recovers,PGOODwillbeassertedagain.Butthereisabuilt-inhysteresis.SeeVpwrgdintheElectricalCharacter-isticsTable.TheaboveinformationisalsoavailableinPowerGoodTruthTable.

WhentheinternalpowergoodMOSFETisturnedon,thePGOODpinwillbepulledtoground.Whenitisturnedoff,thePGOODpinfloats(open-drain).TheonresistanceofthepowergoodMOSFETisabout15kΩ.

DynamicVIDChange

Duringnormaloperation,ifChannel1seesachangeintheVIDpattern,aNEWVIDsignalwillbeissued.UponseeingtheNEWVIDsignal,powergoodsignalwillbedeasserted,UVPandOVPofChannel1willbedisabledtemporarily,andChannel1goesthroughaspecialsteptoquicklyramptheoutputvoltagetothenewvalue.

Ifthenewoutputvoltageishigherthantheoldvoltage,Channel1willrelyonthecontrollooptochangetheoutputvoltage.Ifthenewvalueislowerthantheoldone,thetopFETisgoingtoremainoffwhilethebottomFETisgoingtoremainon.Thiswillcausetheoutputcapacitortodischargethroughtheinductor.The0-CROSSING/NEGATIVECUR-RENTLIMITcomparatorwilldetectfornegativeovercurrent,eveniftheLM2633isinpulse-skipmode.Whenthenegativecurrentlimitisreached,bottomFETwillbeturnedoff,forcingtheinductorcurrenttoflowthroughthebodydiodeofthetopFETtotheinputsupply.Whennextclockcyclecomes,thebottomFETwillbeturnedonagain,anditwillnotbeturnedoffuntilthenegativecurrentlimitisreachedagain.Duringthisprocess,iftheoutputvoltagegoesbelowthenewvolt-age,theNEWVIDsignalwillbedeasserted.Atthistime,powergoodfunctionwillbereleased,OVPandUVPwillbeenabledandthebottomFETwillbeturnedoff.ThenormalcontrollooptakesoveraftertheoutputvoltagedroopsbelowthenewDACvoltage.

Internal5VSupply

Theinternal5VsupplyisgeneratedfromtheVINvoltagethroughaninternallinearregulator.This5Vsupplyismainlyforinternalcircuitryuse,butcanalsobeusedexternally(throughtheVLIN5pin)forconvenience.Atypicaluseofthis5Vissupplyingthebootstrapcircuitryfortopdriversandsupplyingthevoltageneededbythebottomdrivers(throughtheVDDxpins).Butsincethis5Visgeneratedbyalinearregulator,itmayhurtthelightloadefficiency,especiallywhenVINvoltageishigh.Soifthereisaseparate5Vavailablethatisgeneratedbyaswitchingpowersupply,itmaybeagoodideatousethat5VtopowerthebootstrapcircuitryandtheVDDxpinsforbetterefficiencyandlessthermalstressontheLM2633.

Inshutdownmode,theVLIN5pinwillgoto5.5V.SoitisrecommendednottousethisvoltageforpurposesotherthanthebootstrapcircuitryandVDDxpins.

Whenthepowerstageinputvoltagecanbeguaranteedtobewithin4.5Vto5.5V,theVLIN5pincanbetiedtotheVINpindirectly.Inthismode,all5VcurrentsaredirectlycomingfrompowerstageinputrailVINandpowerlossduetotheinternallinearregulationisnolongeranissue.

outputvoltagewillnotbeaffectedunlesstheUVLOmethodisusedtoreleasethelatch.IfthelinearchannelcausesaUVPevent,thentheICentersShutDownLatchState.Iflaterthefaultatthelinearchannelisremoved,thelinearchannelwillrecover,buttheICwillstillbeinthelatchstate.Over-voltageProtection

Thisprotectionfeatureisimplementedinthetwoswitchingchannelsandnotinthelinearchannel.RefertoTable1.Aslongasthereisatleastoneswitchingchannelenabled,andtheLM2633isnotinfaultstate,anovervoltageeventateitherofthetwoswitchingchannels’outputwillcausesys-temtoentertheShutDownLatchState.

However,iftheovervoltageeventhappensonlyonChannel1afteradynamicVIDchangesignalisissuedandbeforethechangecompletes,thesystemwillnotentertheShutDownLatchState.SeetheDynamicVIDChangesection.Under-voltageProtection

TheUVPfeatureisimplementedinallthreechannels.

IftheUV_DELAYpinispulledtoground,thentheunder-voltageprotectionfeatureisdisabled.Otherwise,ifacapaci-torisconnectedbetweentheUV_DELAYpinandground,theUVPisenabled.AssumeUVPisenabledandthesystemisnotinfaultstate.Ifaswitchingchannelisenabled,anditssoftstarttimeoutsignal(sstox,seesoftstartsection)isasserted,thenanundervoltageeventattheoutputofthatchannelwillcausethesystemtoentertheShutDownLatchState.

However,iftheundervoltageeventhappensonlyonChan-nel1afteradynamicVIDchangesignalisissuedandbeforethechangecompletes,thesystemwillnotentertheShutDownLatchState.SeetheDynamicVIDChangesection.Forthelinearchannel,ifthereisatleastoneswitchingchannelon,andatleastonesoftstarttimeoutsignalhasbeenissued,andifthesystemisnotinFaultState,thenanundervoltageeventatthelinearregulatoroutputwillcausethesystemtoenterShutDownLatchState.

WhentheLM2633reactsonanundervoltageevent,a5µAcurrentwillbechargingthecapacitorconnectedtotheUV_DELAYpinandwhenitsvoltageexceeds2.1V,thesystemimmediatelyentersShutDownLatchState.

Fordetails,seetheblockdiagramandShutDownLatchTruthTable.

PowerGoodFunction

Thepowergoodfunctionisageneralindicationofthehealthoftheregulators.ThereisaninternalMOSFETtiedfromthePGOODpintoground.PowergoodsignalisassertedbyturningoffthatMOSFET.

TheinternalpowergoodMOSFETwillnotbeturnedonunlessatleastoneofthefollowingoccurs:

1.Thereisanoutputovervoltageeventinatleastoneof

theswitchingchannels.

2.Theoutputvoltageofanyofthethreechannelsisbelow

thepowergoodlowerlimit,regardlessofON/SSxpinvoltagelevel.

3.WheneverChannel1isgoingthroughadynamicVID

change.

4.Systemisintheshutdownmode.5.Systemisinthefaultstate.

6.Systemisintheshutdownlatchstate.

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24

DesignProcedures

CPUCore/GTLBusPowerSupplyNomenclature

LM2633DesignProcedures

(Continued)

ESR-EquivalentSeriesResistance.

Loadingtransient-aloadtransientwhentheloadcurrentgoesfromminimumloadtofullload.

Unloadingtransient-aloadtransientwhentheloadcurrentgoesfromfullloadtominimumload.C-regulatoroutputcapacitance.D-dutycycle.f-switchingfrequency.

Inlim-negativecurrentlimitlevel.Iilim-ILIMxpincurrent.

Iirrm-maximuminputcurrentrippleRMSvalue.Iload-loadcurrent.

Irip-outputinductorpeak-to-peakripplecurrent.

ThedesignproceduresthatfollowaregenerallyappropriateforboththeCPUcoreandtheGTLbuspowersupplies,althoughemphasisisplacedontheformer.Whenthereisadifferencebetweenthetwo,itwillbepointedout.

OutputCapacitorSelection

Typeofoutputcapacitors

DifferenttypeofcapacitorsoftenhavedifferentcombinationsofcapacitanceandESR.High-capacitancemulti-layerce-ramiccapacitors(MLCs)haveverylowESR,typically12mΩ,butalsorelativelylowcapacitance-upto100µF.TantalumcapacitorscanhavefairlylowESR,suchas18mΩ,andprettyhighcapacitance-upto1mF.AluminumcapacitorscanhaveveryhighcapacitanceandfairlylowESR.OSCONcapacitorscanachieveESRvaluesthatareevenlowerthanthoseofMLCs’whilehavingahighercapacitance.Tutorialonloadtransientresponse

Skiptothenextsubsectionwhenaquickdesignisdesired.ThecontrolloopoftheLM2633canbemadefastenoughsothatwhenaworst-caseloadtransienthappens,dutycyclewillsaturate(meaningitjumpstoeither0%orDmax).Ifthecontrolloopisfastenough,theworstsituationforaloadtransientwillbethatthetransienthappenswhenthefollow-ingthreearealsohappening.One,presentPWMpulsehasjustfinished.Two,inputvoltageisthehighest.Three,theloadcurrentgoesfrommaximumdowntominimum(referredtoasanunloadingtransient).Figure2showshowinductorcurrentchangesduringaworst-caseloadtransient.Thereasonsareasfollows.InamobileCPUapplication,theinput/outputvoltagedifferential,whichisappliedacrosstheinductorduringaloadingtransient,ishigherthantheoutputvoltage,whichisappliedacrosstheinductorduringanun-loadingtransient.

±δ%-CPUcorevoltageregulationwindow.±λ%-LM2633initialDACtolerance.

∆Vc_s-maximumallowedCPUcorevoltageexcursiondur-ingaloadtransient,asderivedfromCPUspecifications.∆Ic_s-maximumloadcurrentchangeduringaloadtransient,asspecifiedbytheCPUmanufacturer.L-inductanceoftheoutputinductor.

Re-totalcombinedESRofoutputcapacitors.

Re_s-maximumallowedtotalcombinedESRoftheoutputcapacitors,asderivedfromCPUloadtransientspecifica-tions.

Rilim-currentlimitadjustmentresistance.SeeCurrentSens-ingandCurrentLimiting.

tmax-maximumalloweddynamicVIDtransitiontime.tpeak-timefortheCPUcorevoltagetoreachitspeakvalueduringanunloadingtransient.

Vin-inputvoltagetotheswitchingregulators.

Vn-nominaloutputvoltage.

Vold-nominalCPUcorevoltagebeforedynamicVIDchange.

Vnew-nominalCPUcorevoltageafterdynamicVIDchange.Vrip-peak-to-peakoutputripplevoltage.

General

Designingapowersupplyinvolvesmanytradeoffs.Agooddesignisusuallyadesignthatmakesgoodtradeoffs.To-day’ssynchronousbuckregulatorstypicallyrunata200kHzto300kHzswitchingfrequency.Beyondthisrange,switchinglossbecomesexcessive,andbelowthisrange,inductorsizebecomesunnecessarilylarge.TheLM2633hasafixedop-eratingfrequencyof250kHzwhenVINvoltageisbelowabout17V,andhasdecreasedfrequencywhenVINvoltageexceeds17V.SeeActiveFrequencyControlsection.

InamobileCPUapplication,boththeCPUcoreandtheGTLbusexhibitlargeandfastloadcurrentswings.Theloadcurrentslewrateduringsuchatransientisusuallywellbeyondtheresponsespeedoftheregulator.Tomeettheregulationspecification,specialconsiderationsshouldbegiventothecomponentselection.Forexample,thetotalcombinedESRoftheoutputcapacitorsmustbelowerthanacertainvalue.Alsobecauseofthetightregulationspecifica-tion,onlyasmallbudgetcanbeassignedtoripplevoltage,typicallylessthan20mV.Itisfoundthatstartingfromagivenoutputvoltageripplewilloftenresultinfewerdesignitera-tions.

20000806

FIGURE2.Worst-caseLoadTransient

Thatmeanstheinductorcurrentchangesslowerduringanunloadingtransientthanduringaloadingtransient.Theslowertheinductorcurrentchangesduringaloadtransient,thehigheroutputcapacitanceisneeded.Thatiswhyanunloadingtransientistheworstcase.IftheloadtransienthappenswhenthepresentPWMpulsehasjustfinished,theinductorcurrentwillbethehighest,whichmeanshighestinitialchargingcurrentfortheoutputcapacitors.Finally,thehighertheinputvoltage,thehighertheinductorripplecur-rentandthehighertheinitialchargingcurrentfortheoutputcapacitors.

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LM2633OutputCapacitorSelection

(Continued)

Thetotalchangeinoutputvoltageduringsuchaloadtran-sientis:

(3)∆Vc=∆Vr+∆VqFromFigure4itcanbetoldthat∆Vcwillreachitspeakvalue

atsomepointintimeandthenitisgoingtodecrease.Thelargertheoutputcapacitanceis,theearlierthepeakwillhappen.Ifthecapacitanceislargeenough,thepeakwilloccuratthebeginningofthetransient,i.e.,∆Vcwilldecreasemonotonicallyafterthetransienthappens.Tofindthepeakposition,letthederivativeof∆Vcgotozero,andtheresultis:

20000807

FIGURE3.LoadTransientSpec.Violation

Becausetheresponsespeedoftheregulatorisslowcom-paredtoatypicalCPUloadtransient,theregulatorhastorelyheavilyontheoutputcapacitorstohandletheloadtransient.TheinitialovershootorundershootiscausedbytheESRoftheoutputcapacitors.Howtheoutputvoltagerecoversafterthatinitialexcursiondependsonhowfasttheoutputinductorcurrentrampsandhowlargetheoutputcapacitanceis.SeeFigure3.IfthetotalcombinedESRoftheoutputcapacitorsisnotlowenough,theinitialoutputvoltageexcursionwillviolatethespecification,see∆Vc1.IftheESRislowenough,butthereisnotenoughoutputcapacitance,outputvoltagewillhavetoomuchanextraexcursionandtraveloutsidethespecificationwindow,beforeitreturnstoitsnominalvalue,see∆Vc2.

(4)

Thetargetistofindthecapacitancevaluethatwillyield,attpeak,a∆Vcthatequals∆Vc_s.Bypluggingtpeakexpressionintothe∆VCexpressionandequatingthelatterto∆Vc_s,thefollowingformulaisobtained:

(5)

NoticeitisalreadyassumedthetotalESRisnogreaterthanRe_sotherwisethetermunderthesquarerootwillbeanegativevalue.

20000813

FIGURE5.Re=Re_svsReTheallowedoutputvoltageexcursionduringaloadtransientis:

20000808

FIGURE4.DeltaOutputVoltageComponentsDuringaloadtransient,thedeltaoutputvoltage∆Vchastwochangingcomponents.OneisthedeltavoltageacrosstheESR(∆Vr),theotheristhedeltavoltagecausedbythegainedcharge(∆Vq).Bothdeltavoltageschangewithtime.For∆Vr,theequationis:

(1)

andfor∆Vq,theequationis:

(6)

Example:Vn=1.35V,δ%=7.5%,λ%=1.4%,Vrip=20mV

(2)

Sincetheripplevoltageisincludedinthecalculationof∆Vc_s,theinductorripplecurrentshouldnotbeincludedintheworst-caseloadcurrentexcursion.Thatis,theworst-caseloadcurrentexcursionshouldbesimply∆Ic_s.

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LM2633OutputCapacitorSelection

(Continued)

MaximumESRcalculation

Nomatterhowmuchcapacitancethereis,ifthetotalcom-binedESRisnotlessthanacertainvalue,theloadtransientrequirementwillnotbemet.

ThemaximumallowedtotalcombinedESRis:

Generallyspeaking,Cmaxdecreaseswithdecreasingtmax,InlimandIload,butwithincreasingvoltagestep.Powerlossinoutputcapacitors

Inatypicalbuckregulator,theripplecurrentintheinductor(andthustheoutputcapacitors)issosmallthatitcausesverylittlepowerloss.Theequationforcalculatingthatlossis:

(7)

Example:∆Vc_s=72mV,∆Ic_s=10A.ThenRe_s=7.2mΩ.MaximumESRcriterioncanbeusedwhenthecapacitanceishighenough,otherwisemorecapacitorsthanthenumberdeterminedbythiscriterionshouldbeused.Minimumcapacitancecalculation

InaCPUcoreoraGTLbuspowersupply,theminimumoutputcapacitanceistypicallydictatedbytheloadtransientrequirement.Ifthereisnotenoughcapacitance,theoutputvoltageexcursionwillexceedthemaximumallowedvalueevenifthemaximumESRrequirementismet.Theworst-caseloadtransientisanunloadingtransientthathap-penswhentheinputvoltageisthehighestandwhenthetopFEThasjustbeenturnedoff.Thecorrespondingminimumcapacitanceiscalculatedasfollows:

(10)

Example:Irip=4.3A,Re=7mΩ.

(11)

OutputInductorSelection

Thesizeoftheoutputinductorcanbedeterminedfromtheassignedoutputripplevoltagebudgetandtheimpedanceoftheoutputcapacitorsatswitchingfrequency.Theequationtodeterminetheminimuminductancevalueisasfollows:

(8)

NoticeitisalreadyassumedthetotalESRisnogreaterthanRe_s,otherwisethetermunderthesquarerootwillbeanegativevalue.

Example:Re=6mΩ,Vn=1.35V,∆Vc_s=72mV,∆Ic_s=10A,L=2µH

(12)

wheremin(Vin_max,17V)meansthesmallerofVin_maxand17V.ThereasonthistermisnotsimplyVin_maxisthattheswitchingfrequencydroopswithincreasingVinwhenVinishigherthan17V.SeeActiveFrequencyControl.

Intheaboveequation,Reisusedinplaceoftheimpedanceoftheoutputcapacitors.Thisisbecauseinmostcases,theimpedanceoftheoutputcapacitorsattheswitchingfre-quencyisveryclosetoRe.Inthecaseofceramiccapacitors,replaceRewiththetrueimpedance.

Example1:Vin_max=21V,Vn=1.6V,Vrip=26mV,Re=6mΩ,f=250kHz.

Generallyspeaking,CmindecreaseswithdecreasingRe,∆Ic_s,andL,butwithincreasingVnand∆Vc_s.Maximumcapacitancecalculation

ThissubsectionappliestoChannel1/CPUcorepowersupplyonly.

IfthereisaneedtochangetheCPUcorevoltagedynami-cally(seeDynamicVIDChange),therewillbeamaximumoutputcapacitancerestriction.Iftheoutputcapacitanceistoolarge,itwilltaketoomuchtimefortheCPUcorevoltagetoramptothenewvalue,violatingthemaximumtransitiontimespecification.Theworst-casedynamicVIDchangeisonethattakesthelargeststepdownatnoload.Themaxi-mumcapacitanceasdeterminedbythewayLM2633imple-mentstheVIDchangecanbecalculatedasfollows:

Example2:Vin_max=18V,Vn=1.35V,Vrip=20mV,Re=6mΩ,f=250kHz.

(9)

Example:tmax=100µs,Inlim=20A,Vold=1.6V,Vnew=1.35V,Iload=0.

27

Theactualselectionprocessusuallyinvolvesseveralitera-tionsofalloftheabovesteps,fromripplevoltageselection,tocapacitorselection,toinductancecalculations.BoththehighestandthelowestCPUcorevoltagesandtheirloadtransientrequirementsshouldbeconsidered.Ifaninduc-tancevaluelargerthanLminisselected,makesuretheCminrequirementisnotviolated.Priorityshouldbegiventopa-rametersthatarenotflexibleormorecostly.Forexample,ifthereareveryfewtypesofcapacitorstochoosefrom,itmay

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LM2633OutputInductorSelection

(Continued)

beagoodideatoadjusttheinductancevaluesothatarequirementof3.2capacitorscanbereducedto3capaci-tors.

Inductorripplecurrentisoftenthecriterionforselectinganoutputinductor.However,intheCPUcoreorGTLbusapplication,itisusuallyoflowerpriority.Thatispartlybe-causethestringentoutputripplevoltagerequirementauto-maticallylimitstheinductorripplecurrentlevel.Itisnever-thelessagoodideatodoublechecktheripplecurrent.Theequationis:

current.InthecaseoftwoFETsinparallel,multiplythecalculatedonresistanceby4toobtaintheonresistanceforeachFET.InthecaseofthreeFETs,thatnumberis9.SinceefficiencyisveryimportantinamobilePC,havingthelowestonresistanceisusuallymoreimportantthanfullyutilizingthethermalcapacityofthepackage.Soitisprobablybettertofindthelowest-RdsFETfirst,andthendeterminehowmanyareneeded.

Example:Tj_max=100˚C,Ta_max=60˚C,Rθja=60˚C/W,Vin_max=21V,Vn=1.6V,andIload_max=10A.

(13)

wheremin(Vin_max,17V)meansthesmallerofVin_maxand17V.

Whatismoreimportantistheripplecontent,whichisdefinedbyIrip_max/Iload_max.Generallyspeaking,aripplecontentoflessthan50%isok.Toohigharipplecontentwillcausetoomuchlossintheinductor.

Example:Vin_max=21V,Vn=1.6V,f=250kHz,L=1.7µH.

Ifthelowest-on-resistanceFEThasaRds_maxof10mΩ,thentwocanbeusedinparallel.ThetemperatureriseoneachFETwillnotgotoTj_maxbecauseeachFETisnowdissipat-ingonlyhalfofthetotalpower.

Alternatively,two22mΩFETscanbeusedinparallel,witheachFETreachingTj_max.ThismaylowertheFETcost,butwilldoublethebottomswitchpowerloss.

TopFETSelection

ThetopFEThastwotypesofpowerlosses-theswitchinglossandtheconductionloss.Theswitchinglossmainlyconsistsofthecross-overlossandthebottomdiodereverserecoveryloss.Itisratherdifficulttoestimatetheswitchingloss.Ageneralstartingpointistoallot60%ofthetopFETthermalcapacitytoswitchingloss.Thebestwaytofindoutisstilltotestitonbench.TheequationforcalculatingtheonresistanceofthetopFETisthus:

Ifthemaximumloadcurrentis14A,thentheripplecontentis4.3A/14A=30%.

Whenchoosingtheinductor,thesaturationcurrentshouldbehigherthanthemaximumpeakinductorcurrent.TheRMScurrentratingshouldbehigherthanthemaximumloadcurrent.

MOSFETSelection

BottomFETSelection

Duringnormaloperations,thebottomFETisturnedonandoffatalmostzerovoltage.SoonlyconductionlossispresentinthebottomFET.ThebottomFETpowerlosspeaksatthemaximuminputvoltageandloadcurrent.ThemostimportantparameterwhenchoosingthebottomFETistheonresis-tance.Thelesstheonresistance,thelessthepowerloss.TheequationforthemaximumallowedonresistanceatroomtemperatureforagivenFETpackage,is:

(15)

whereTj_maxisthemaximumallowedjunctiontemperatureintheFET,Ta_maxisthemaximumambienttemperature,Rθjaisthejunction-to-ambientthermalresistanceoftheFET,andTCisthetemperaturecoefficientoftheonresistancewhichistypically4000ppm/˚C.

Example:Tj_max=100˚C,Ta_max=60˚,Rθja=60˚C/W,Vin_min=14V,Vn=1.6V,andIload_max=10A.

(14)

whereTj_maxisthemaximumallowedjunctiontemperatureintheFET,Ta_maxisthemaximumambienttemperature,Rθjaisthejunction-to-ambientthermalresistanceoftheFET,andTCisthetemperaturecoefficientoftheonresistancewhichistypically4000ppm/˚C.

Ifthecalculatedonresistanceissmallerthanthelowestvalueavailable,multipleFETscanbeusedinparallel.Ifthedesigncriterionistousethehighest-RdsFET,thentheRds_maxofeachFETcanbeincreasedduetoreduced

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28

SincetheswitchinglossusuallyincreaseswithbiggerFETs,choosingatopFETwithamuchsmalleronresistancesometimesmaynotyieldnoticeablelowertemperatureriseandbetterefficiency.

ItisrecommendedthatthepeakvalueoftheVdsofthetopFETdoesnotexceed200mVwhenthetopFETconducts,otherwisetheCOMPxpinvoltagemayreachitshighclampvalue(2V)andcauselossofregulation.

LM2633CurrentLimitSetting

Whatisactuallymonitoredandlimitedisthepeakdrain-sourcevoltageofthetopFETwhenitisconducting.Theequationforcurrentlimitresistorisasfollows:

tweenthetwochannels’inputcurrentpulses.TheequationforcalculatingthemaximumtotalinputrippleRMScurrentistherefore:

(17)

whereI1ismaximumloadcurrentofChannel1,I2isthemaximumloadcurrentofChannel2,D1isthedutycycleofChannel1,andD2isthedutycycleofChannel2.

(16)

whereIload_limisthedesiredloadcurrentlimitlevelandIilim_ministheminimumsinkcurrentattheILIM1pin.ThiscalculatedRilimvalueguaranteesthattheminimumcurrentlimitwillnotbelessthanIload_lim.

Example:Iload_lim=16A,Irip_max=4.3A,Rds_max=18mΩ,Tj_max=100˚C,Iilim_min=8µA.

Example:Iload_max_1=6.8A,Iload_max_2=2A,D1=0.09,andD2=0.1.

Itisrecommendedthata1%tolerantresistorbeusedanditsresistanceshouldnotbelowerthanthecalculatedvalue.

InputCapacitorSelection

Inatypicalbuckregulatorthepowerlossintheinputcapaci-torsismuchlargerthanthatintheoutputcapacitors.Thatisbecausethecurrentflowingthroughtheinputcapacitorsisofsquare-waveshapeandthepeak-to-peakmagnitudeisequaltoloadcurrent.TheresultisalargerippleRMScurrentintheinputcapacitors.

ThefactthatthetwoswitchingchannelsoftheLM2633are180˚outofphasehelpsreducetheRMSvalueoftheripplecurrentseenbytheinputcapacitors.Thatwillhelpextendinputcapacitorlifespanandresultinamoreefficientsys-tem.InamobileCPUapplication,boththeCPUcoreandGTLbusvoltagesareratherlowcomparedtotheinputvoltage.Thecorrespondingdutycyclesarethereforelessthan50%,whichmeanstherewillbenoover-lappingbe-

Chooseinputcapacitorsthatcanhandle1.97ArippleRMScurrentathighestambienttemperature.Theinputcapacitorsshouldalsomeetthevoltageratingrequirement.Inthiscase,aSANYOOSCONcapacitor25SP33M,oraTaiyoYudenceramiccapacitorTMK325BJ475,willmeetbothre-quirements.

Comparison:Ifthetwochannelsareoperatinginphase,therippleRMSvaluewouldbe2.52A.Theequationforcalculat-ingrippleRMScurrenttakesthesameformastheoneabovebutthemeaningsofthevariableschange.I1isthesumofthemaximumloadcurrents,D1isthesmallerdutycycleofthetwo,D2isthedifferencebetweenthetwodutycycles,andI2isthemaximumloadcurrentofthechannelthathaslargerdutycycle.

Figure6showshowthereductionofinputrippleRMScur-rentbroughtbythe2-phaseoperationvarieswithloadcur-rentratioanddutycycles.Fromtheplots,itcanbeseenthatthebenefitofthe2-phaseoperationtendstomaximizewhenthetwoloadcurrentstendtobeequal.Anotherconclusionisthattheratioincreasesrapidlywhenonechannel’sdutycycleiscatchingupwiththeotherchannel’sandthenbe-comesalmostflatwhentheformerexceedsthelatter.SotheabsoluteoptimaloperatingpointintermsofinputrippleisatD1=D2=0.5andIload_max_1=Iload_max_2,whentheinputripplecurrentiszerofor2-phaseoperation.

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LM2633InputCapacitorSelection

(Continued)

20000884

FIGURE6.InputRippleRMSCurrentRatio:2-phasevs.In-phase

ControlLoopDesign

SamllSignalModel

ThebuckregulatorsmallsignalmodelisshowninFigure7.Themodelisobtainedbyapplyingthecurrent-controlledPWMswitchderivedbyVorperianandbyomittingportionsthatareirrelevantinabucktopology.

20000838

FIGURE7.SmallSignalModelofBuckRegulatorsInthemodel,theDCoutputconductanceofthePWMswitchis:

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LM2633ControlLoopDesign

(Continued)

γ=C(R+Re)+go(CRRe+L)+CsR

δ=1+goR

(30)(31)

(18)

Where

D’=1−D

(19)

Forareasonabledesign,theoutputfilterhaslargeattenua-tionatlargecomplexfrequencies(i.e.largesvalues).Atsvalueswhere1/sCissmallerthanRe,thepowerstagecanbereducedtotheoneshowninFigure8.

(20)

200008D5

Se=Vm•f

(21)

FIGURE8.SimplifiedPowerStageatHighFrequenciesThetransferfunctioncanbere-writtenas:

(22)

Ri=Rds•ρ(23)

Seisthecorrectionrampslope,Snistheon-timeslopeofthecurrentsensewaveform,Vmisthepeak-peakvalueofthecorrectionramp,fisthePWMfrequency,Vinisinputvoltage,Riisthetransferresistancefrominductorcurrenttorampvoltage,RdsisthetopFETon-resistanceandρisthegainofthecurrentsenseamplifier.

Thecoefficientofthefirstcurrentsourceis:

(32)

Where

(33)

(24)

andthecoefficientofthesecondcurrentsourceis:

(34)

AlltheRetermsareomittedinthedenominatorbecausetheirvaluesarenegligiblecomparedtootherterms.

Sincethedenominatorofthecontrol-outputtransferfunctionisathird-orderpolynomial,anditscoefficientsarepositiverealnumbers,thetransferfunctioneitherhasonerealpoleandtwocomplexpolesthatarecomplexconjugatesorhasthreerealpoles.Thusitcanbeapproximatelywritteninthefollowingformat:

(25)

TheoutputcapacitanceofthePWMswitchis:

(26)

TheDCresistanceoftheFETswitchesandoftheinductorisnotincludedherebecauseitsvalueisusuallymuchsmallerthantheloadresistance.

Where

Control-OutputTransferFunction

Thecontrol(COMPxpin)voltageinapeak-currentmodeschemesuchasthatoftheLM2633isthecurrentcommand.Atanyinstantthatvoltagedeterminestheleveloftheinduc-torcurrent(fromanaverage-modelpointofview).Thecontrol-outputtransferfunctionisadescriptionofthesmall-signalbehaviorofthepowerstageandisobtainedbylettingthesmallsignalcomponentoftheinputvoltagebezero.Theexpressionforthecontrol-outputtransferfunctionis:

(35)

(36)

and

(37)

where

(27)

Where

α=LCsC(R+Re)

β=goLC(R+Re)+Cs(CRRe+L)

(28)(29)

31

(38)

and

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LM2633ControlLoopDesign

(Continued)

(39)

Thevalueoffpcanbedeterminedbycomparingthedenomi-natorsofEquation(35)andEquation(27).Theresultis:

(40)

Fromtheaboveexpressions,itcanbeseenthatthecontrol-outputtransferfunctionhasthreepolesandonezero.Ofthethreepoles,oneisarealpole(fp)thatislocatedatlowfrequency,theothertwoareeithercomplexconju-gatesthatarelocatedathalftheswitchingfrequency(fn),orareseparatedrealpoles,dependingontheQvalue.WhenQvalueislessthan0.5,thetwohighfrequencypoleswillbecometworealpoles.

FromEquation(34)itcanbetoldthatQwillbecomenega-tivewhenmc<1/(2D’).AnegativeQvaluemeansanunstablesystembecausethecontrol-outputtransferfunctionwillhavearight-half-planepole.

Example:L=1.5µH,C=2mF,Re=9mΩ,Rds=10mΩ,Vin=10V,Vout=1.6V,R=0.4Ω.ForLM2633,f=250kHz,Se=0.25V,ρ=5.

20000863

FIGURE9.ExampleControl-OutputTransferFunction

BodePlotItshouldbenotedthatloadresistanceonlychangesthelowfrequencygain.Thiscausesthelocationofthelowfre-quencypoletochangewithload.

FrequencyCompensationDesign

Thegeneralpurposetocompensatetheloopistomeetstaticanddynamicperformancerequirementswhilemain-tainingstability.Loopgainiswhatisusuallycheckedforsmall-signalperformance.Loopgainisequaltotheproductofcontrol-outputtransferfunction(orso-called’plant’)andtheoutput-controltransferfunction(i.e.thecompensationnetworktransferfunction).Differentcompensationschemesresultindifferenttrade-offsamongstaticaccuracy,transientresponsespeedanddegreeofstability,etc.

Generallyspeakingitisagoodideatohavealoopgainslopethatis−20dB/decadefromaverylowfrequencytowellbeyondcross-overfrequency.Thecross-overfrequencyshouldnotexceedone-fifthoftheswitchingfrequency,i.e.50kHzinthecaseofLM2633.Thehigherthebandwidth,thepotentiallyfastertheloadtransientresponsespeed.How-ever,ifthedutycyclesaturatesduringtheloadtransient,thenfurtherincreasingthesmallsignalbandwidthwillnothelp.InthecontextofCPUcoreorGTLbuspowersupply,asmall-signalbandwidthof20kHzto30kHzshouldbesuffi-cientifoutputcapacitorsarenotjustMLCs.

Sincethecontrol-outputtransferfunctionusuallyhasverylimitedlowfrequencygain(seeFigure9),itisagoodideatoplaceapoleinthecompensationatzerofrequency,sothatthelowfrequencygainespeciallytheDCgainwillbeverylarge.AlargeDCgainmeanshighDCregulationaccuracy(i.e.DCvoltagechangeslittlewithloadorlinevariations).Therestofthecompensationschemedependshighlyontheplantshape.IfatypicalshapesuchasshowninFigure9isassumed,thenthefollowingcanbedonetocreatea−20dB/decaderoll-offoftheloopgain.

Placethefirstzeroatfp,thesecondpoleatfz,andthesecondzeroatfn,thentheresultingloopgainplotwillbeof−20dB/decslopefromzerofrequencyuptofn(halftheswitchingfrequency).

Rj=10mΩx5=50mΩSe=0.25Vx250kHz=62.5mV/µs

fn=250kHz÷2=125kHz

TheresultinggainplotisshowninFigure9astheasymptoticplot.TheplotsoftheactualgainandphaseascomputedbyEquation(27)arealsoshown.

Figure10showsthegainplotofsuchatwo-poletwo-zero(moreaccurately,alag-lag)compensationnetwork,wherefz1,fz2andfp2arethefirstzero,secondzeroandsecondpolefrequencies.Thefirstpolefp1islocatedatzerofre-quency.

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LM2633ControlLoopDesign

VID4:00000000001000100001100100001010011000111010000100101010010110110001101011100111110000100011001010011101001010110110101111100011001110101101111100111011111011111

VDAC(V)2.001.951.901.851.801.751.701.651.601.551.501.451.401.351.30NOCPU1.2751.2501.2251.2001.1751.1501.1251.1001.0751.0501.0251.0000.9750.950.9250.900

R125k25k25k25k25k25k25k25k25k25k25k25k25k25k25k25k12.5k12.5k12.5k12.5k12.5k12.5k12.5k12.5k12.5k12.5k12.5k12.5k12.5k12.5k12.5k12.5k

(Continued)

TABLE5.R1andR2Valuesvs.VID

R217.1k18.4k17.4k21.4k19.3k22.0k22.1k30.0k24.5k27.3k26.0k34.6k29.3k36.0k36.4k64.3k23.2k25.7k24.5k32.1k27.5k33.3k33.6k56.2k39.6k47.4k43.4k75.0k53.7k81.8k83.7k

r=

R2/(R1+R2)

0.410.420.410.460.430.470.470.550.490.520.510.580.540.590.590.720.650.670.660.720.690.730.730.820.760.790.780.860.810.870.871

FIGURE11.CompensationNetwork

Thegainofthecompensationnetworkcanbecalculatedasthefollowing.IftheESRzerofrequencyfzishigherthanthelowfrequencypolefp,thenthereshouldbea−20dB/decadesectionfromfp(310Hz)tofz(8.8kHz)intheplantgainplot,suchasshowninFigure9.Findthefrequencywherethissection(ortheextensionofthissection)crosses0dBbyusingthefollowingequation:

fc_o=M•fp(41)Ifthedesiredlooptransferfunctioncross-overfrequencyis

fc_c,thenthegainofthecompensationnetworkatfpshouldbe:

2000086520000864

FIGURE10.2-Pole2-Zero(lag-lag)NetworkAsymptotic

GainPlotToachievethegainshapeinFigure10,ZcinFigure7shouldtaketheformoftwoRCbranchesinparallel,asshowninFigure11.Inthescheme,C1andR3formthefirstzerofz1,C2andR3formthesecondpolefp2,andC2andR4formthesecondzerofz2.

∞

Thesignalpathfromoutputvoltagetocontrolvoltageisthefeedbackpath.Ittypicallycontainsavoltagedivider,anerroramplifierandacompensationnetwork.ThoseareshownInFigure7asR1,R2,thegmamplifier,andZc.ForChannel1oftheLM2633,sinceanR-2Rladdernetworkisused,R1andR2valueschangewiththeVIDsetting.Forinformationregardingtheirvaluesandratios,refertoTable5.ForChan-nel2,R1andR2aresimplytheexternalvoltagedividerresistors.

(42)

TodeterminethecomponentvaluesinFigure11,thefollow-ingequationscanbeused:

(43)

whereBisthedesiredgainatfz1,andgmisthetranscon-ductanceoftheerroramplifier.

(44)

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LM2633ControlLoopDesign

(Continued)

(45)

(46)

Backtothepreviousexample.LetB=K,fz1=fp,fp2=fz,fz2=fn,then:

fc_o=5.1x310Hz=1581Hz

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FIGURE13.ExampleLoopTransferFunctionIfashorterrecoverytimeisdesiredduringaloadtransient,fz1canbeincreasedsothatthegainofthelooptransferfunctionbecomeshigher.However,trynottoletfz1behigherthanthedesiredcross-overfrequency,otherwisephasemar-gincanbetoolow.Figure14showsasituationwherefz1isplacedatahigherfrequencythanthefp,whichresultsina−40dB/decsectionbeforethecross-overfrequency.Noticethephasemarginislower.

ThecorrespondingBodeplotsofthecompensationnetworkandthelooptransferfunctionareshowninFigure12andFigure13respectively.

200008D6

FIGURE14.HigherLowFrequencyGain

Sometimestheslowtransientresponseiscausedbythecurrentsourceandsinkcapabilityoftheerroramplifier.Reducingthevalueofthecompensationcapacitorhelps,butmakesurethesmall-signalloopisstable.

Thepowerstagecomponentselectioncanbesignificantlydifferentfromtheexamplevalues.Figure15showshowthetwohighfrequencypolesofacurrent-mode-controlbuckregulatorchangewiththeQvalue.

20000876

FIGURE12.ExampleCompensationTransferFunctionItcanbeseenfromFigure13thatthecrossoverfrequencyis20kHz,andthephasemarginisabout84degrees.

OnethingthatshouldbepointedoutisthisBodeplotisonlyforthe0.4Ωload.Thatis,whenloadcurrentis4A.Ifloadcurrentislowerthan4A,theportionofthegainplotfromthecorrespondingfpto310Hzwillbe−40dB/dec.Ifloadcurrentishigherthan4A,thentheportionofthegainplotfrom310Hztofpwillbeflat.However,thisusuallydoesnothavemucheffectonthecross-overfrequencyandphasemarginbecauseithappensatlowfrequencies.

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LM2633ControlLoopDesign

(Continued)

(48)

whereH(s)isthecompensationtransferfunctiondefinedby:

(49)

ItcanbeseenfromEquation(47)thatifmcisequalto1/(2D’)+0.5,thentheopen-loopaudiosusceptibilityiszero.Unfortunately,thetransferfunctionisrathersensitivetothevalueofmcaroundthecriticalvalueandthusthisphenom-enonisoflittlevalue.

20000878

FIGURE15.HowControl-OutputTransferFunction

ChangeswithQValuesWhenQishigherthan0.5,therewillbeadouble-poleathalftheswitchingfrequencyfn.WhenQislowerthan0.5,thedouble-poleisdampedandbecomestwoseparatepoles.ThelowertheQvalueis,thefartherapartthetwopolesare.WhenQistoolow(suchasQ=0.05orlower),oneofthetwohighfrequencypolesmaymovewellintothelowfre-quencyregion.WhenQistoohigh(suchasQ=5orhigher),therewillbesignificantpeakingathalftheswitchingfre-quencyandthephasewillrapidlygoto−180˚nearit.Thistypicallyresultsinalowercross-overfrequencysothatthepeakingintheloopgainiswellbelowthe0dBline.

Qisafunctionofdutycycleandthedeepnessoftherampcompensation(mc).SeeEquation(34).Thelargerthedutycycle,thehighertheQvalue.Thedeepertherampcompen-sation,thelowertheQvalue.Whentheinductorcurrentrampistoomuchsmallerthanthecompensationramp,oneofthetwohighfrequencypoleswillmovefarintothelowfrequencyregionandformadouble-polewiththeexistinglowfrequencypolefp.Thatmakesitavoltage-modecontrol.Therampcompensationbecomesdeeperwheninductanceisincreased,orinputvoltageisdecreased,orsenseresis-tanceisdecreased.

InthecaseofChannel1ofLM2633,ifL=1to3µH,Vin=5to24V,Vo=0.925to2V,Rds=5to20mΩ,theQvaluewillbebetween0.65and0.2.

AudioSusceptibility

Audiosusceptibilityisthetransferfunctionfrominputtooutput.Inatypicalpowersupplydesign,itisdesirabletohaveasmuchattenuationinthattransferfunctionaspos-siblesothatnoiseappearingattheinputhaslittleeffectontheoutput.Theopen-loopaudiosusceptibilitygivenbythemodelinFigure7is:

20000882

FIGURE16.ExampleAudioSusceptibilityGainTheopen-loopandclosed-loopaudiosusceptibilityofthepreviousexampleisshowninFigure16.Itcanbetold,bothfromthemodelandfromEquation(47),thatopen-loopgainofaudiosusceptibilityisjustalevelshiftoftheloopgain.Closed-loopaudiosusceptibilitystartstodepartfromitsopen-loopcounterpartwhenfrequencydropsbelowthecross-overfrequency.

AdjustingtheOutputVoltagesoftheSwitchingChannels

Channel1outputvoltageisnormallyadjustedthroughtheVIDpins.Channel2outputvoltageisadjustedthroughanexternalvoltagedivider,asshowninFigure17.

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FIGURE17.SettingtheCh2OutputVoltageTheequationtofindthevalueofR2whenR1hasbeenselectedis:

(47)

Theclosed-loopaudiosusceptibilityissimply:

(50)

whereVfb2isequaltotheinternalreferencevoltagecon-nectedtothenon-invertinginputoftheChannel2error

35

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LM2633ControlLoopDesign

(Continued)

amplifier,andIfb2isthecurrentdrawnbytheFB2pin.TheVfb2andIfb2haveatypicalvalueof1.24Vand18nArespectively.

Example:Vout2=1.5V,R1=10kΩ.

Sinceanop-ampisanactivedevice,paycloseattentiontoitsstartupandshutdownbehavior.Makesurethatitdoesnotcreateaproblemduringthosetimes.

DesigningaPowerSupplywithoutaLoadTransientSpecification

Manytimestheloadtransientresponseofabuckregulatorisnotacriticalissue.Inthatcase,theselectionofthepowerstagecomponentscanstartfromtheinductorripplecurrent.Choosingthepeak-to-peakripplecurrenttobe30%ofthemaximumloadcurrentisoftenagoodstartingpoint.Thentheinductancevaluecanbedeterminedbyripple,switchingfrequencyandinputandoutputvoltages.ByrearrangingEquation(13),theinductancevaluecanbecalculatedasfollows:

(51)

Tocalculatethetotalsystemtolerance,usethefollowingequation:

(52)

whereφisthetoleranceoftheChannel2referencevoltage,andσisthetoleranceoftheresistors.

Example:Vout2=3.3V,feedbackresistorshavea±1%tolerance.

(54)

Example:Vin_max=21V,Vn=1.6V,Iload_max=10A.

(53)

Thatmeansthe3.3Voutputvoltagewillhavea±2.96%toleranceoverthe(LM2633die)temperaturerangeof0˚Cto125˚C.

Channel2outputvoltageshouldnotgoabove6Vinpulse-skipmode.ThatisbecausetheSENSE2pincannottakeavoltagehigherthan6V.However,ifforce-PWMop-erationisthechosenoperatingmode,thentheSENSE2pincanbegroundedandtherewillbenolimitationtoChannel2outputvoltage.

IfthedesiredChannel1voltageishigherthan2V,anop-ampandavoltagedividercanbeusedtoexpandthevoltagerange,asshowninFigure18.

Theoutputcapacitorscanbechosenbasedontheoutputvoltageripplerequirement.Ifthereisnospecificrequire-ment,thena±1%ripplelevelmaybeagoodstartingpoint.Theequationfordeterminingtheimpedanceoftheoutputcapacitorsis:

(55)

IftheESRzerofrequencyofthecapacitorislowerthantheswitchingfrequency,suchasthecaseofaluminum,tantalumandOSCONcapacitors,thentheoutputcapacitorsarecho-senbytheESRvalue.Otherwise,suchasinthecaseofceramiccapacitors,theoutputcapacitorsarechosenbythecapacitance.Theequationis:

(56)

Basicallymakesurethattheproductoftheimpedanceofthecapacitorsandtheripplecurrentdoesnotexceedtheripplevoltagerequirement.

Example:Vn=1.6V,Irip=3A.

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FIGURE18.HowtoMakeVOUT1HigherThan2VItisrecommendedthattheVIDxpinsbealltiedtogroundsothattheDACissetat2.00V.Thatwillreducethetotaltolerance.TheequationsusedtocalculateChannel2’sfeed-backresistorsandtotaltolerancestillhold,exceptthatthereferencevoltageVfb1is2.00Vinsteadof1.24V.Channel1canoperateonlyinforce-PWMmodewhenitisconfiguredasFigure18.

(57)

Ifceramiccapacitorsarepreferred,thentheminimumca-pacitanceis:

(58)

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LM2633ControlLoopDesign

(Continued)

Ifaluminum,tantalumorOSCONcapacitorsaregoingtobeused,makesurethecombinedESRisnotgreaterthan10.6mΩ.

Dependingontheapplication,adifferentprioritymaybeassignedtotheselectionofcomponents.Forexample,toachievea10.6mΩcombinedESR,itwouldrequire6low-ESRtantalumcapacitors,whichcanbequiteexpensive.Iftheinductorsizeisallowedtoexpand,thenahigherinductancevaluecanbeusedsothatripplecurrentisre-ducedandimpedanceofthecapacitorattheswitchingfre-quencycanbehigher.Itisoftennecessarytogothroughseveraliterationsbeforeareasonablecombinationoftheinductorandcapacitorsisachieved.

Noticetheaboveprocedureisgivenwithoutanyconsider-ationofaloadtransient,whetherexpectedorunexpected.Thepowersupplydesignermaybetemptedtousea100µFceramiccapacitorastheonlyoutputcapacitorintheaboveexample.Thatmaybefineinadesignthathasaverystaticload.However,shouldtherebealargefaultloadcurrent(whichisnotenoughtotriggerUVP)andiflaterthatcondi-tionissuddenlylifted,theoutputmayseeasevereovervoltage.AlthoughtheLM2633willshutdownimmediatelyuponseeingtheover-voltageevent,theloadcouldhavebeendamagedalready.Anotherconcernwithpureceramicoutputcapacitorsissoftstart.Itmaybenecessarytoin-creasethesoftstarttimesothattherewillbeminimumovershootattheendofsoftstart.Sowhenalargeinduc-tanceandasmallcapacitancearechosen,careshouldbegiventotheabovesituations.

Iftheloadcurrentgoesfromoneleveltoanotherduringnormaloperations,adesignwithlesscapacitancetendstohavemoreoutputvoltageexcursionandrecovermoreslowlythanonewithmorecapacitance.Fromthetime-domainviewpoint,thatisbecauselesscapacitanceislesseffectiveanenergybufferwhentheloadcurrentistemporarilydifferentfromtheinductorcurrent.Fromthefrequency-domainviewpoint,thatisbecausetheoutputim-pedanceoftheregulatorishigher.

Forpowersuppliesthatdon’thaveastringentloadtransientrequirement,polymeraluminumcapacitorscanbeusedaswellaslow-ESRtantalumcapacitors.Thesepolymeralumi-numcapacitorsaresurfacemount,long-life,ignitionfreeandtypicallyhaveverylowESRvalues.Forexample,CornellDubilier’sESREandESRDpolymeraluminumchipcapaci-torshaveESRvalueaslowas6mΩandcapacitanceupto270µF(http://www.cornell-dubilier.com).

Panasonicalsooffersspecialtypolymeraluminumcapaci-tors.Panasonic’sUEseriesofferscapacitanceupto270µF,andvoltageratingupto8VDC.

FortheTypicalApplicationcircuit,ifthereisnostringentloadtransientrequirementonChannel1,C2canbereplacedbyasinglepolymeraluminumcapacitor,suchasESRE271M02RfromCornellDubilier.Thefrequencycom-pensationshouldbe:C14=4.7nF,R9=7.5kΩ.C15andR10arenotnecessary.Noticethatthevoltageratingofthatcapacitorisonly2VDC.

DesigningAroundthePulse-SkipMode

IftheFPWMpinispulledtologichigh,theLM2633operatesinpulse-skipmode.Inthismode,whentheloadislightenough,theLM2633startstoskippulses.SeePulse-SkipModeinOperationDescriptions.

Inpulse-skipmode,theapparentswitchingfrequencyislowerthanthefrequencytheregulatorwouldrunatifitwereinforce-PWMmode.Theactualfrequencydependsontheload,thelightertheloadthelowerthefrequency.

Theloadatwhichpulse-skippingstartstohappencanbedeterminedfromthefollowingformula:

(59)

Example:Irip=3A.

Sincethecriticalloadcurrentcompletelydependsontheinductorripplecurrent,theinductancevaluecannotbearbi-traryifaccuratecontrolofthevalueofthecriticalloadisdesired.

WhentheFPWMpinispulledhigh,theregulatorentersthediscontinuousconductionmode(DCM)whentheloadislightenoughsothattheinductorcurrentgoestozerobeforetheendofeachswitchingcycle.ThecriticalloadcurrentvaluefortheregulatortoenterDCMis:

(60)

NoticeinDCMmodetheFETsstillswitcheveryclockcyclebutthedutycycleshrinksasloadcurrentdecreases.WhentheloadcurrentgoesbelowIload_skip,theregulatorentersthepulse-skipmode.SotheDCMregionisaverynarrowone.

So,whenthepeak-peakripplecurrentis3A,theDCMhappensonlywhenloadcurrentfallsinthe1.1Ato1.5Arange.Abovethatrange,theregulatorisincontinuouscon-ductionmode(CCM),andbelowthatrange,theregulatorrunsinpulse-skipmode.

DesigningaLinearRegulatorwithChannel3

Channel3oftheLM2633canbeusedtodriveanexternalNPNtransistorandprovidelinearregulation.SeeFigure19.

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FIGURE19.Channel3ControllinganLDO

Theoutputvoltageisadjustedthroughthevoltagedivider,andtheequationis:

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LM2633ControlLoopDesign

(Continued)

TheerroramplifierofChannel3hasaDCgainof83dB,andaunity-gainbandwidthof200kHz.SeetheplotsinFigure21.

(61)

whereVfb3isequaltothereferencevoltageconnectedtothenon-invertinginputoftheerroramplifierandhasatypicalvalueof1.24V,andIfb3isthebiascurrentdrawnbytheFB3pinandhasatypicalvalueof70nA.

Example:Theintendedoutputvoltageis2.5V.FindtheappropriateR2valueifR1ischosentobe10.0kΩ.

(62)

TheG3voltagecannotexceed4V,andtheG3currentsourcingcapabilitydecreaseswithincreasingG3pinvolt-age.Seethetypicalcurves.Itissuggestedthatthemaxi-mumoutputvoltagedoesnotexceed3VwhenanNPNpasstransistorisused.IfanN-channelFETistobeused,makesuretheFETcanbefullyturnedonbeforeG3goesto4V.TherearetwofactorstoconsiderwhenselectingQ1.FirstistheDCcurrentgainβ,secondispowerdissipation.

Foracertainloadcurrent,thelowertheβvalue,themorebasecurrentisnecessarytomaintainregulation.SincethebasecurrentcomesfromVINpinthroughinternallinearregulation,alargebasecurrentsignificantlyincreasespowerconsumptionintheLM2633andhurtslight-loadefficiency,particularlywhenVINisrelativelyhigh.Thereforeatransistorwithalargeβvalueispreferred.

ThemaximumpowerconsumptioninQ1is:

Ploss=Iload_max•(Vin2_max−Vout3_min)(63)

Example:Theinputvoltageofthelinearregulatoris3.3V±5%,themaximumloadcurrentis150mA,andtheoutputvoltageis2.5V.SinceChannel3oftheLM2633hasa±2%toleranceovertemperature,andthevoltagedividercontrib-utesanother±1%,sothetotaloutputvoltagetoleranceis±3%.SeeEquation(52)forthecalculationoftotaltolerancewhenavoltagedividerisused.

Ploss=150mAx(3.3Vx1.05−2.5Vx0.97)=156mWIftheambienttemperatureis65˚Corless,aSOT-23pack-ageshouldbeabletohandlethismuchpower.

SinceChannel3affectsUVP,ifitisnottobeused,properterminationofthepinsshouldbemade.OnegoodwayistotieFB3toVLIN5,andtieOUT3andG3togetherandleavethemfloating.SeeFigure20.

20000895

FIGURE21.VFB3-to-VG3TransferFunction(theoretical)ItisnoteasytomodeltheloopfrequencyresponseofanNPNlinearregulator.Thebestwayisstilltomeasuretheloopgainunderdifferentloadconditionsonbench.Asareferencepoint,foranLDOsetat2.5VthatusesanMMBT2222asthepasstransistor,a1µFceramicastheoutputcapacitorandata170mAload,thebandwidthisabout107kHz,withaphasemarginof71˚andagainmarginofabout10dB.

Thehigherthebandwidth,thelesstheoutputcapacitanceisneededtohandletheloadtransient.However,formostapplications,stabilityistheonlyconcern.

PCBLayoutGuidelines

Itisextremelyimportanttofollowtheguidelinesbelowtoensureacleanandstableoperation.1.Useafour-layerPCB.

2.KeeptheFETsasclosetotheICaspossible.

3.Keepthepowercomponentsontherightside(pins25

through48)oftheICandlow-powercomponentsontheleftside.

4.Analoggroundandpowergroundshouldbeseparate

planesandshouldbeconnectedatasinglepoint,pref-erablyatthePGNDxandGNDpinsanddirectlyunder-neaththeIC.

5.TheVDDxpindecouplingcapacitorshouldbecon-nectedtothepowergroundplane.

6.Inputceramiccapacitorsshouldbeplacedverycloseto

theFETsandtheirconnectionstothedrainofthetopFETandtothesourceofthebottomFETshouldbeasshortaspossibleandshouldnotgothroughpowerplaneorgroundplane.

7.HDRVx,SWxtracesshouldbeasclosetoeachotheras

possibletominimizenoiseemission.Ifthesetwotracesarelongerthan2centimeters,theyshouldbefairlywide,suchas50mil.

8.KeepKSxtraceasshortaspossible.Otherwise,usea

traceof50milorwider.

9.ILIMxtraceshouldbekeptawayfromnoisynodessuch

astheswitchnode.

10.ItispreferabletohaveashorterandwiderFBxtrace

thanalongerandnarrowerone.

38

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FIGURE20.WhenCh.3isNotinUse

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LM2633PCBLayoutGuidelines

(Continued)

11.VLIN5pindecouplingcapacitorshouldbeconnectedto

thelocalanalogground.12.Compensationcomponentsshouldbeplacedcloseto

theIC,within1to2centimeters.

13.Channel3shouldusetheanalogground,notthepower

ground,toavoidpotentialnoisecouplingfromtheswitchingchannels.AnexampleofthepowerstagelayoutisshowninFigure22.

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FIGURE22.PCBLayoutExample

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LM2633AdvancedTwo-PhaseSynchronousTripleRegulatorControllerforNotebookCPUsPhysicalDimensions

unlessotherwisenoted

inches(millimeters)

48-LeadTSSOPPackageOrderNumberLM2633MTDNSPackageNumberMTD48

LIFESUPPORTPOLICY

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