MISOMOSIGPIO1GPIO0S31
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S20S30S29S28S27S26S25S24S23S22S21S19Figure 2-1 Package Pin Configuration (QFN48) Table 2-1 Package Signal Descriptions (QFN48) Pin # 1 2 3 4 5 6 7 8 9 10 11 43~12 44 45 46 47 48 Pin Name V18_2 GND VDD IOVDD RESET SS/SCL Description Core power, connect to 4.7uF capacitor Ground Power supply I/O power supply System reset signal input, active low SPI: slave select I2C: serial clock SPI: serial clock I2C: serial data SPI: master input/slave output SPI: master output/slave input General purpose input/output General purpose input/output Touch sensor input Ground Connect capacitor tenfold to touch pad capacitor Connect capacitor tenfold to touch pad capacitor Common mode voltage, connect to 0.1uF Core power, connect to 4.7uF capacitor SCK /SDA MISO MOSI GPIO1 GPIO0 S0~S31 GND C2 C1 VCM V18_1 Ver 1.0 Page 4/13 2010/07/19 ST1332 Figure 2-2 Package Pin Configuration (QFN40) Table 2-2 Package Signal Descriptions (QFN40) Pin # 1 2 3 4 5 6 7 8 9~36 37 38 39 40 Pin Name V18_2 GND VDD RESET SS/SCL Description Core power, connect to 4.7uF capacitor Ground Power supply System reset signal input, active low SPI: slave select I2C: serial clock SPI: serial clock I2C: serial data General purpose input/output General purpose input/output Touch sensor input, except S0, S17, S18, S19 Connect capacitor tenfold to touch pad capacitor Connect capacitor tenfold to touch pad capacitor Common mode voltage, connect to 0.1uF Core power, connect to 4.7uF capacitor SCK /SDA GPIO1 GPIO0 S1~S31 C2 C1 VCM V18_1 Ver 1.0 Page 5/13 2010/07/19 ST1332 3 3.1 SYSTEM MANAGEMENT Power Down In power down mode, all of the clocks of ST1332 are stopped, including internal oscillator. The way to exit power down mode is by a reset. In power down mode, ST1332 consumes a few current, less than 5uA. 3.2 Reset 3.2.1 Master Reset Master can reset ST1332 through RESET pin. RESET pin is low active and needs hold low for 1us to take effect. Figure 3-1 RESET Pin Low Pulse Width 3.2.2 Power On Reset ST1332 provides an on-chip Power-On-Reset (POR) circuit to detect power-on and to reset internal logic before VDD reached the pre-determined POR threshold voltage. Under VDD=3.3V, the POR threshold voltage is set to be about 2.1V. Sometimes, when the VDD is power-off and quickly power-on again, there might be cases that the POR will work improperly and internal reset might not be generated. For this reason, it is also highly recommended user should have a long time between power-off and next power-on to ensure proper start-up. The time depends on actual system board environment and how much decoupling capacitors between power and ground. User has to take into account this effect during board level design. 3.2.3 Watch Dog Timer Reset The watchdog timer (WDT) protects the ST1332 from incorrect code execution over a long period of time by causing a system reset when the watchdog timer overflows as a result of a failure of software to feed the timer prior to the timer reaching its terminal count. Ver 1.0 Page 6/13 2010/07/19 ST1332 4 4.1 DIGITAL INTERFACE SPI Interface (Slave) SPI provides full-duplex, synchronous serial communication between ST1332 and host controller. It is a 4-wire protocol, consisting of slave select(SS/SCL), clock(SCK/SDA), master data input/slave data output(MISO), and master data output/slave data input(MOSI). The SPI can only be configured to operate as salve in ST1332 and clock is always provided by master. Data is sampled at rising edge of the clock. Figure 4-1 SPI Waveform 4.2 I2C Slave Interface ST1332 equipped with I2C provide two wires, serial data (SDA) and serial clock (SCL), to carry information transfers at up to 400 kbit/s(Fast mode). ST1332 plays a slave role in I2C transfer. Both SDA and SCL are bidirectional lines, connected to IOVDD via pull-up resistors. All transactions begin with a START (S) and can be terminated by a STOP (P). 7-Bit address follows START to recognize device. Each bye is 8-bit length and followed by an acknowledge bit. A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. Read Figure 4-2 I2C Waveform Ver 1.0 Page 7/13 2010/07/19 ST1332 5 5.1 ELECTRICAL CHARACTERISTIC DC Electrical Characteristics Table 5-1 System DC Electrical Characteristics Condition: VDD = IOVDD = 3.3V, TA = 25°C, unless otherwise specified. Parameter VDD IOVDD Operating Current Power Down Current Input High Voltage Input Low Voltage Input Pull Up Resistor Output Driving Current Output Sinking Current Low Voltage Reset Symbol Min. VVDD VIOVDD INML IPD VIH VIL RPU IDRV ISINK VLVR 2.4 1.8 - - - - - - - - Typ. Max. Unit 3.3 3.3 6 5 1.9 1.3 56 40 70 1.6 3.6 3.6 - - - - - - - - V V mA uA V V Condition KOhm mA mA V VOH=0.7xVDD VOL=0.3xVDD 5.2 AC Electrical Characteristics Figure 5-1 I2C Fast Mode Timing Table 5-2 I2C Fast Mode Timing Characteristic Conditions: VDD = IOVDD = 3.3V, GND = 0V, TA = 25°C Symbol fSCL tLOW tHIGH tf tr Parameter Rating Min. Typ. 0 - 1.3 - 0.6 - - - - - 0.6 0.6 - - Max. 400 - - 300 300 - - Unit kHz us us ns ns us us SCL clock frequency Low period of the SCL clock High period of the SCL clock Signal falling time Signal rising time Set up time for a repeated START tSU_STA condition Hold time (repeated) START condition. tHD_STA After this period, the first clock pulse is generated Ver 1.0 Page 8/13 2010/07/19 tSU_DAT Data set up time tHD_DAT Data hold time tSU_STO Set up time for STOP condition Bus free time between a STOP and tBUF START condition Cb Capacitive load for each bus line 100 0 0.6 1.3 - - - - - - - 0.9 - - 400 ns us us us pF ST1332 Figure 5-2 SPI Timing Table 5-3 SPI Timing Characteristic Conditions: VDD = IOVDD = 3.3V, GND = 0V, TA = 25°C Symbol tSS_SCK tCYC tDS tDH tDD tSCK_SS st Parameter SS falling to 1 SCK falling SCK cycle time Data setup time prior SCK rising Data hold time after SCK rising MISO data output delay from SCK falling SCK rising to SS rising Rating Min. Typ. Max. 41.6 - - - 83 - 2 - - 2 - - 10 - - 41.6 - - Unit ns ns ns ns ns ns Ver 1.0 Page 9/13 2010/07/19 ST1332 6 APPLICATION CIRCUITS Ver 1.0 Page 10/13 2010/07/19 ST1332 7 PACKAGE DIMENSION Figure 7-1 Package Dimension (QFN48) Ver 1.0 Page 11/13 2010/07/19 ST1332 Figure 7-2 Package Dimension (QFN40) Ver 1.0 Page 12/13 2010/07/19 ST1332 8 0.1 1.0 REVISION DESCRIPTION First release Remove “Preliminary” REVISION PAGE DATE 2010/04/26 2010/07/19 The above information is the exclusive intellectual property of Sitronix Technology Corp. and shall not be disclosed, distributed or reproduced without permission from Sitronix. Sitronix Technology Corp. reserves the right to change this document without prior notice and makes no warranty for any errors which may appear in this document. Sitronix products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where products failure could result in injury, or loss of life, or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. Preliminary Ver 1.0 Page 13/13 2010/07/19
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